A three-step procedure utilizing only two test structures for de-embedding transistor from on-wafer S-parameter measurements

15th International Conference on Microwaves, Radar and Wireless Communications, MIKON - 2004

Volumn 2, Issue , 2004, Pages 674-677

  Myslinski, Maciej ^a   Wiatr, Wojciech ^b   Schreurs, Dominique ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; CAPACITANCE; COST EFFECTIVENESS; ELECTRIC PROPERTIES; ELECTRODES; FREQUENCY DOMAIN ANALYSIS; MATHEMATICAL MODELS; OPTICAL INTERCONNECTS; RADIO SYSTEMS; SHORT CIRCUIT CURRENTS;

DE-EMBEDDING TRANSISTOR; DEVICE UNDER TEST (DUT); PARASITIC EFFECT; VECTOR NETWORK ANALYZER (VNA);

BIPOLAR TRANSISTORS;

EID: 11244340634     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. M. Myslinski, D. Schreurs, and W. Wiatr, "Development and verification of a non-linear look-up table model for RF silicon BJTs", Proc. 10th European Gallium Arsenide and Other Semiconductors Application Symposium, Milan, Italy, pp. 93-96, 2002.
2. A. Fraser, R. Gleason, E.W. Strid, "GHz On-Silicon-Wafer Probing Calibration Methods", Proc. IEEE 1988 Bipolar Circuits and Technology Meeting, Minneapolis, USA, pp. 154 - 157, 1988.
3. E.P. Vandamme, D. Schreurs, C. Van Dinther, "Improved Three-step De-embedding Method to Accurately Account for the Influence of Pad Parasitics in Si On-Wafer RF Test-Structures", IEEE Trans. Electron Devices, Vol. 48, No.4, pp. 737 - 742, 2001.
4. T.E. Kolding, "A Four-Step Method for De-Embedding Gigahertz On-Wafer CMOS Measurements", IEEE Trans. Electronic Devices, Vol. 47, No. 4, pp. 734 - 739, 2000.