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Volumn , Issue , 2004, Pages 191-198

Multi-objective optimization of a parameterized VLIW architecture

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN SPACE EXPLORATION (DSE); INSTRUCTION LEVEL PARALLELISM (ILP); PARETO-OPTIMAL CONFIGURATIONS;

EID: 11244289376     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EH.2004.1310830     Document Type: Conference Paper
Times cited : (7)

References (17)
  • 2
    • 11244258774 scopus 로고    scopus 로고
    • An evolutionary approach for pareto-optimal configurations in soc platforms
    • K. A. Pulishers, editor
    • G. Ascia, V. Catania, and M. Palesi. An evolutionary approach for pareto-optimal configurations in soc platforms. In K. A. Pulishers, editor, SOC Design Methodologies, 2002.
    • (2002) SOC Design Methodologies
    • Ascia, G.1    Catania, V.2    Palesi, M.3
  • 4
    • 85015962264 scopus 로고    scopus 로고
    • Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques
    • Feb.
    • L. Benini, A. Macii, and M. Poncino. Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques. ACM Transactions on Embedded Computing Systems, 2(1), Feb. 2003.
    • (2003) ACM Transactions on Embedded Computing Systems , vol.2 , Issue.1
    • Benini, L.1    Macii, A.2    Poncino, M.3
  • 5
    • 0005320209 scopus 로고    scopus 로고
    • Architectural level power/performance optimization and dynamic power estimation
    • Nov.
    • G. Cai and C. H. Lim. Architectural level power/performance optimization and dynamic power estimation. In Cool Chips Tutorial colocated with MICRO32, pages 90-113, Nov. 1999.
    • (1999) Cool Chips Tutorial Colocated with MICRO32 , pp. 90-113
    • Cai, G.1    Lim, C.H.2
  • 8
    • 0036705159 scopus 로고    scopus 로고
    • System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip
    • Aug.
    • T. Givargis, F. Vahid, and J. Henkel. System-level exploration for Pareto-optimal configurations in parameterized System-on-a-Chip. IEEE Transactions on Very Large Scale Integration Systems, 10(2):416-422, Aug. 2002.
    • (2002) IEEE Transactions on Very Large Scale Integration Systems , vol.10 , Issue.2 , pp. 416-422
    • Givargis, T.1    Vahid, F.2    Henkel, J.3
  • 15
    • 0036042330 scopus 로고    scopus 로고
    • Multi-objective design space exploration using genetic algorithms
    • Stanley Hotel, Estes Park, Colorado, USA, May 6-8
    • M. Palesi and T. Givargis. Multi-objective design space exploration using genetic algorithms. In Tenth International Symposium on Hardware/Software Codesign, Stanley Hotel, Estes Park, Colorado, USA, May 6-8 2002.
    • (2002) Tenth International Symposium on Hardware/Software Codesign
    • Palesi, M.1    Givargis, T.2
  • 17
    • 0003450887 scopus 로고    scopus 로고
    • CACTI 3.0: An integrated cache timing, power, and area model
    • COMPAQ Western Research Lab, Palo Alto, California 94301 USA
    • P. Shivakumar and N. P. Jouppi. CACTI 3.0: An integrated cache timing, power, and area model. Technical report, COMPAQ Western Research Lab, Palo Alto, California 94301 USA, 1999.
    • (1999) Technical Report
    • Shivakumar, P.1    Jouppi, N.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.