Construction of a fault-tolerant voter for N-modular redundancy

Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)

Volumn 87, Issue 12, 2004, Pages 62-71

  Takaesu, Kohtaro ^a   Yoshida, Takeo ^a  

^a UNIVERSITY OF THE RYUKYUS   (Japan)

Author keywords

ADR; Duplex system; Majority voter; N modular redundancy system; TMR

Indexed keywords

DATA ACQUISITION; DECODING; ENCODING (SYMBOLS); ERROR DETECTION; LOGIC CIRCUITS; REDUNDANCY; RELIABILITY; SYSTEMS ANALYSIS;

ALTERNATE DATA ENTRY (ADR); DUPLEX SYSTEM; FAULT TOLERANT VOTER; N-MODULAR REDUNDANCY SYSTEMS; TRIPLE MODULAR REDUNDANCY (TMR);

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 11044238825     PISSN: 8756663X     EISSN: None     Source Type: Journal    
DOI: 10.1002/ecjb.20136     Document Type: Article

References (9)

1. Mori H, Kambara J. Fault tolerant tree processor using voting. Trans IEICE 1992;J75-D-I:780-787.
2. Kanagawa N, et al. Fault tolerant computer system using new voting pattern. Trans IEICE 1990;J73-D-I:109-116.
3. Nanya T. Fault tolerant computers. Ohm Press; 1991.
4. Shedletsky JJ. Error correction by alternate-data retry. IEEE Trans Comput 1978;27:106-112.
5. Kotani K et al. Design of ALU using error-correctable checksum code based on temporal redundancy. Trans IEICE 1983;J66-D:243-250.
6. Hasegawa Y, Naito A. Fault tolerant circuit based on ADR. Trans IEICE 1983;J66-D:198-205.
7. Yoshida T. Masking double faults in combinatorial circuits using temporal redundancy and Hamming code. Tech Rep IEICE 1997;FTS97-45.
8. Naito A, Fujinawa O. Design of fault-free combinatorial circuit using ADR. Trans IEICE 1986;J69-D:1154-1164.
9. Takaesu T, Yoshida T. Design of high-reliability voter using ADR. Tech Rep IEICE 1999;FTS99-38.