A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection

IEEE International Conference on Neural Networks - Conference Proceedings

Volumn 4, Issue , 2004, Pages 2619-2624

  Asai, Tetsuya ^a   Kanazawa, Yusuke ^a   Hirose, Tetsuya ^a   Amemiya, Yoshihito ^a  

^a HOKKAIDO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; MOS DEVICES; NEURAL NETWORKS; PATTERN RECOGNITION;

EXCITATORY POSTSYNAPTIC POTENTIAL (EPSP); INHIBITORY POSTSYNAPTIC POTENTIAL (IPSP); SYNAPSES; SYNCHRONY DETECTION;

CMOS INTEGRATED CIRCUITS;

EID: 10944239608     PISSN: 10987576     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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