Silicon device scaling to the sub-10-nm regime

Science

Volumn 306, Issue 5704, 2004, Pages 2057-2060

  Ieong, Meikei ^a   Doris, Bruce ^b   Kedzierski, Jakub ^a   Rim, Ken ^a   Yang, Min ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL GEOMETRY; ELECTRIC CURRENT CARRYING CAPACITY (CABLES); LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; MOS DEVICES; NANOTECHNOLOGY; STRAIN;

DEVICE SCALING; GATE LENGTHS; NANOMETER MEASUREMENTS; SILICON DEVICES;

SEMICONDUCTOR DEVICE MANUFACTURE;

NANOTECHNOLOGY; SILICON;

CRYSTAL STRUCTURE; ELECTRIC CONDUCTIVITY; ELECTRON TRANSPORT; ELECTRONICS; NANOTECHNOLOGY; PRIORITY JOURNAL; REVIEW; SEMICONDUCTOR;

EID: 10844253101     PISSN: 00368075     EISSN: None     Source Type: Journal    
DOI: 10.1126/science.1100731     Document Type: Review

References (33)

1. Semiconductor Industry Association, International Technology Roadmap for Semiconductors (2003); available at http://public.itrs.net.
2. R. H. Dennard et al., IEEE J. Solid-State Circuits 9, 256 (1974).
3. Y. Taur, IEEE Spectrum 36, 25 (1999).
4. The performance of bulk MOSFETs is often degraded in a stack configuration. This is known as the reverse body effect. In SOI technology, the body is isolated from other terminals; therefore, the reverse body effect can be avoided.
5. H. Ieong, J. Kedzierski, Z. Ren, B. Doris, T. Kanarsky, H.-S. P. Wong, Extended Abstract of the 2002 International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, 17 to 19 September 2002, pp. 136-137.
6. B. Doris et al., International Electron Device Meeting (IEDM) Tech. Dig. 2002, 267 (2002).
7. J. Kedzierski et al., IEDM Tech. Dig. 2002, 247 (2002).
8. A halo implant is an ion implantation technique that places impurity dopants next to the junction tip to prevent SCEs without substantially increasing the total amount of impurity dopants in the channel. Because of the halo implant, devices can be scaled to shorter gate lengths before notable SCE sets in.
9. B. Doris et al., IEDH Tech. Dig. 2003, 631 (2003).
10. Z. Ren et al., IEDM Tech. Dig. 2002, 51 (2002).
11. H.-S. P. Wong, IBM J. Res. Dev. 46, 133 (2002).
12. M. Ieong, H.-S. P. Wong, E. Nowak, J. Kedzierski, E. Jones, Proc. Third International Symposium on Quality Electronic Design (ISQED) (2002), pp. 492-495.
13. L. Chang et al., Proc. IEEE 91, 1860 (2003).
14. M. Ieong et al., IEDM Tech. Dig. 2001, 441 (2001).
15. K. W. Guarini et al., IEDM Tech. Dig. 2001, 425 (2001).
16. J. M. Hergenrother et al., IEDM Tech. Dig. 1999, 75 (1999).
17. J. Kedzierski et al., IEDM Tech. Dig. 2001, 437 (2001).
18. D. Hisamoto, T. Kaga, Y. Kawamoto, E. Takeda, IEDM Tech. Dig. 1989, 833 (1989).
19. X. Huang et al., IEDM Tech. Dig. 1999, 67 (1999).
20. K. Rim, et al., Symposium on VLSI Technology, Honolulu, HI, 11 to 15 June 2002, pp. 12-13.
21. A. Lochtefeld, D. Antoniadis, IEEE Electron Device Lett. 22, 591 (2001).
22. S. Ito et al., IEDM Tech. Dig. 2000, 247 (2000).
23. G. Scott, J. Lutze, M. Rubin, F. Nouri, M. Manley, IEDM Tech. Dig. 1999, 827 (1999).
24. T. Ghani et al., IEDM Tech. Dig. 2003, 631 (2003).
25. C.-H. Ge et al., IEDM Tech. Dig. 2003, 73 (2003).
26. V. Chan et al., IEDM Tech. Dig. 2003, 77 (2003).
27. K. Goto et al., IEDM Tech. Dig. 2003, 623 (2003).
28. B.-H. Lee et al., IEDM Tech. Dig. 2002, 946 (2002).
29. K. Rim et al., IEDM Tech. Dig. 2003, 49 (2003).
30. M. Yang, IEEE Electron Devices Lett. 24, 339 (2003).
31. M. Yang et al., IEDM Tech. Dig. 2003, 453 (2003).
32. B. Doris et al., Symposium on VLSI Technology, Honolulu, HI, 15 to 19 June 2004, pp. 86-87.
33. The authors are grateful to their IBM colleagues. Fabrication support by the Advanced Semiconductor Technology Center of IBM Microelectronic Division and the Advanced Semiconductor Technology Laboratory of IBM Research are very much appreciated.