A novel process for co-integration of vertical double-gate and planar single-gate MOSFETs

Device Research Conference - Conference Digest, DRC

Volumn 2003-January, Issue , 2003, Pages 49-50

  Masahara, M ^a   Matsukawa, T ^a   Hosokawa, S ^a   Ishii, K ^a   Liu, Yongxun ^a   Tanoue, H ^a   Sakamoto, K ^a   Sekigawa, T ^a   Yamauchi, H ^a   Kanemaru, S ^a   Suzuki, E ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

Author keywords

Circuit optimization; Circuit synthesis; CMOS technology; Etching; Ion implantation; Manufacturing industries; MOSFETs; Nanoelectronics; Scalability; Virtual colonoscopy

Indexed keywords

CMOS INTEGRATED CIRCUITS; ETCHING; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT MANUFACTURE; ION IMPLANTATION; NANOELECTRONICS; SCALABILITY;

CIRCUIT OPTIMIZATION; CIRCUIT SYNTHESIS; CMOS TECHNOLOGY; MANUFACTURING INDUSTRIES; MOSFETS; VIRTUAL COLONOSCOPY;

MOSFET DEVICES;

EID: 10644282595     PISSN: 15483770     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.2003.1226866     Document Type: Conference Paper

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