Chip integration of sea of leads compliant I/O interconnections for the ultimate enabling of chips with low-k interlayer dielectrics

Proceedings - Electronic Components and Technology Conference

Volumn 1, Issue , 2004, Pages 1167-1173

  Bakir, Muhannad S ^a   Dang, Bing ^a   Emery, Richard ^b   Vandentop, Gilroy ^b   Martin, Kevin P ^a   Kohl, Paul A ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP INTEGRATION; LOW-K INTERLAYER DIELECTRICS; MICROGRAPHS; THERMOCOMPRESSION BONDING;

DIELECTRIC MATERIALS; INPUT OUTPUT PROGRAMS; LEAD; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICES; SILICON WAFERS; SOLDERING; THERMAL EXPANSION;

INTERCONNECTION NETWORKS;

EID: 10444288677     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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2. M. Bakir, H. Reed, A. Mule, J. Jayachandran, P. Kohl, K. Martin, T. Gaylord, and J. Meindl, "Chip-to-module interconnections using 'Sea of Leads' technology," MRS Bulletin, vol. 28, no. 1, pp. 61-67, Jan. 2003.
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