A 2-D forward/inverse integer transform processor of H.264 based on highly-parallel architecture

Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004

Volumn , Issue , 2004, Pages 158-161

  Liu, Ling Zhi ^a   Qiu, Lin ^a   Rong, Meng Tian ^a   Jiang, Li ^a  

^a SHANGHAI JIAO TONG UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK DIAGRAMS; HARDWARE MODULES; INTEGER TRANSFORMS; VIDEO IMAGES;

COMPUTER AIDED DESIGN; COMPUTER SOFTWARE; IMAGE COMPRESSION; IMAGE PROCESSING; INTEGER PROGRAMMING; LOGIC GATES; NATURAL FREQUENCIES; PROGRAM PROCESSORS;

COMPUTER ARCHITECTURE;

EID: 10444254739     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1002/0471648272.ch10     Document Type: Conference Paper

References (5)

1. ITU-T Rec, H.264/ISO/IEC 11496-10, "Advanced video coding", Final Committee Draft, Document JVT-G050, March 2003
2. Henrique S. Malvar, et al. "Low-Complexity Transform and Quantization in H.264/AVC". IEEE Transactions on Circuit and Systems for Video Technology, Vol.13, pp. 598-603, July 2003.
3. A.Madisetti, et al. "A 100MHz 2-D 8xg DCT/IDCT Processor for HDTV Applications". IEEE Transactions on Circuit and Systems for Video Technology, Vol.5, pp. 158-165, Apr. 1995
4. Thomas Wiegand, et al. "Overview of the H.264/AVC Video Coding Standard" IEEE Transactions on Circuit and Systems for Video Technology, Vol. 13, pp. 560-576, July 2003.
5. Tu -Chih Wang, et al. " Parallel 4×4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264" in Proc. of 2003 IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, May 2003, pp. 800-803.