A novel CMOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection

International Journal of Robotics and Automation

Volumn 19, Issue 4, 2004, Pages 206-212

  Kanazawa, Yusuke ^a   Asai, Tetsuya ^a   Ikebe, Masayuki ^a   Amemiya, Yoshihito ^a  

^a HOKKAIDO UNIVERSITY   (Japan)

Author keywords

Analog circuit; Depressing synapse; Dynamic synapse; Neuromorphic VLSI; Spiking neuron

Indexed keywords

COMPUTER SIMULATION; DATA PROCESSING; INTEGRATED CIRCUITS; MOS DEVICES; NONLINEAR SYSTEMS; PATTERN RECOGNITION; RELIABILITY; SILICON; TRANSISTORS;

ANALOG CIRCUIT; DEPRESSING SYNAPSE; DYNAMIC SYNAPSE; SPIKING NEURON;

CMOS INTEGRATED CIRCUITS;

EID: 10244222278     PISSN: 08268185     EISSN: None     Source Type: Journal    
DOI: 10.2316/journal.206.2004.4.206-2716     Document Type: Article

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