Solder joint reliability evaluation of chip scale package using a modified Coffin-Manson equation

Microelectronics Reliability

Volumn 44, Issue 2, 2004, Pages 269-274

  Shohji, Ikuo ^a   Mori, Hideo ^b   Orii, Yasumitsu ^b  

^a GUNMA UNIVERSITY   (Japan)

^b IBM JAPAN LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVATION ENERGY; CHIP SCALE PACKAGES; CRACK PROPAGATION; FATIGUE OF MATERIALS; MICROSTRUCTURE; NUMERICAL METHODS; SCANNING ELECTRON MICROSCOPY; SOLDERED JOINTS; STRAIN; THERMAL CYCLING; THERMAL EFFECTS; TIN;

BALL GRID ARRAY (BGA); COEFFICIENT OF THERMAL EXPANSION (CTE); PERSONAL DIGITAL ASSISTANTS (PDA); THERMAL FATIGUE;

MICROELECTRONICS;

EID: 0942299011     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2003.08.015     Document Type: Article

References (11)

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