Technology Scaling Effects on the ESD Design Parameters in Sub-100nm CMOS Transistors

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 507-510

  Boselli, Gianluca ^a   Rodriguez, John ^a   Duvvury, Charvaka ^a   Reddy, Vijay ^a   Chidambaram, P R ^a   Hornung, Brian ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; DIELECTRIC DEVICES; DOPING (ADDITIVES); ELECTRIC BREAKDOWN; ELECTRIC CONDUCTANCE; ELECTRIC RESISTANCE; ENERGY EFFICIENCY; SEMICONDUCTOR JUNCTIONS; SUBSTRATES; TRANSISTORS;

GATE LENGTH TRANSISTORS; TRIGGERING VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0842309769     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. C. Duvvury et al., EOS/ESD Symp. Proceedings, pp. 7-17, 2000.
2. J. Miller et al., EOS/ESD Symp. Proceedings, pp. 308-317, 2000.
3. B. Hornung et al., Symp. On VLSI Technology, paper 7A-3, 2003.
4. V. Gupta et al., EOS/ESD Symp. Proceedings, pp. 161-169, 1998.
5. A. Amerasekera et al., IEDM Tech. Dig., pp. 547-550, 1995.
6. K.-H. Oh et al., IRPS Proceedings, pp. 226-234, 2001.
7. K. Bock et al., EOS/ESD Symp. Proceedings, pp. 95-104, 1999
8. K.-H. Oh et al., IEDM Tech. Dig., pp. 341-344, 2002.