-
1
-
-
0029391690
-
A 40 nm gate length nMOSFET
-
Oct.
-
M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai, "A 40 nm gate length nMOSFET," IEEE Trans. Electron Devices, vol. 42, pp. 1822-1830, Oct. 1995.
-
(1995)
IEEE Trans. Electron Devices
, vol.42
, pp. 1822-1830
-
-
Ono, M.1
Saito, M.2
Yoshitomi, T.3
Fiegna, C.4
Ohguro, T.5
Iwai, H.6
-
2
-
-
0033280895
-
High performance 50-nm physical gate length pMOSFETs by using low temperature activation by re-crystallization scheme
-
K. Tsuji, K. Takeuchi, and T. Mogami, "High performance 50-nm physical gate length pMOSFETs by using low temperature activation by re-crystallization scheme," in Tech. Dig. VLSI Symp., 1999, pp. 9-10.
-
Tech. Dig. VLSI Symp., 1999
, pp. 9-10
-
-
Tsuji, K.1
Takeuchi, K.2
Mogami, T.3
-
3
-
-
0033280391
-
Co salicide compatible 2-step activation annealing process for deca-nano scaled MOSFETs
-
K. Goto, Y. Sambonsugi, and T. Sugii, "Co salicide compatible 2-step activation annealing process for deca-nano scaled MOSFETs," in VLSI Symp. Tech. Dig., 1999, pp. 49-50.
-
VLSI Symp. Tech. Dig., 1999
, pp. 49-50
-
-
Goto, K.1
Sambonsugi, Y.2
Sugii, T.3
-
4
-
-
0033281013
-
65 nm physical gate length NMOSFETs with heavy ion implanted pockets and highly reliable 2nm-thick gate oxide for 1.5 V operation
-
C. Caillat, S. Deleonibus, G. Guegan, S. Tedesco, B. Dal'zotto, M. Heitzmann, F. Martin, P. Mur, B. Marchand, and F. Balestra, "65 nm physical gate length NMOSFETs with heavy ion implanted pockets and highly reliable 2nm-thick gate oxide for 1.5 V operation," in VLSI Symp. Tech. Dig., 1999, pp. 89-90.
-
VLSI Symp. Tech. Dig., 1999
, pp. 89-90
-
-
Caillat, C.1
Deleonibus, S.2
Guegan, G.3
Tedesco, S.4
Dal'zotto, B.5
Heitzmann, M.6
Martin, F.7
Mur, P.8
Marchand, B.9
Balestra, F.10
-
5
-
-
0003899569
-
30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays
-
Dec.
-
R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, and G. Dewey, "30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays," in IEDM Tech. Dig., Dec. 2000, pp. 45-48.
-
(2000)
IEDM Tech. Dig.
, pp. 45-48
-
-
Chau, R.1
Kavalieros, J.2
Roberds, B.3
Schenker, R.R.4
Lionberger, D.5
Barlage, D.6
Doyle, B.7
Arghavani, R.8
Murthy, A.9
Dewey, G.10
-
6
-
-
0034454556
-
45-nm gate length CMOS technology and beyond using steep halo
-
Dec.
-
H. Wakabayashi, M. Ueki, M. Narihiro, T. Fukai, N. Ikezawa, T. Matsuda, K. Yoshida, K. Takeuchi, Y. Ochiai, T. Mogami, and T. Kunio, "45-nm gate length CMOS technology and beyond using steep halo," in IEDM Tech. Dig., Dec. 2000, pp. 49-52.
-
(2000)
IEDM Tech. Dig.
, pp. 49-52
-
-
Wakabayashi, H.1
Ueki, M.2
Narihiro, M.3
Fukai, T.4
Ikezawa, N.5
Matsuda, T.6
Yoshida, K.7
Takeuchi, K.8
Ochiai, Y.9
Mogami, T.10
Kunio, T.11
-
8
-
-
0035872897
-
High-k gate dielectrics: Current status and materials properties considerations
-
G. D. Wilk, R. M. Wallace, and J. M. Anthony, "High-k gate dielectrics: Current status and materials properties considerations," J. Appl. Phys., vol. 89, no. 10, pp. 5243-5275, 2001.
-
(2001)
J. Appl. Phys.
, vol.89
, Issue.10
, pp. 5243-5275
-
-
Wilk, G.D.1
Wallace, R.M.2
Anthony, J.M.3
-
9
-
-
0029336129
-
New α-particle induced soft error mechanism in a three dimensional capacitor cell
-
Y. Oowaki, K. Mabuchi, S. Watanabe, K. Ohuchi, J. Matsunaga, and F. Masuoka, "New α-Particle induced soft error mechanism in a three dimensional capacitor cell," IEICE Trans. Electron., vol. E78-C, no. 7, pp. 845-851, 1995.
-
(1995)
IEICE Trans. Electron.
, vol.E78-C
, Issue.7
, pp. 845-851
-
-
Oowaki, Y.1
Mabuchi, K.2
Watanabe, S.3
Ohuchi, K.4
Matsunaga, J.5
Masuoka, F.6
-
10
-
-
0035718371
-
2 as high-k gate dielectrics with polysilicon gate electrode
-
Dec.
-
2 as high-k gate dielectrics with polysilicon gate electrode," in IEDM Tech. Dig., Dec. 2001, pp. 455-458.
-
(2001)
IEDM Tech. Dig.
, pp. 455-458
-
-
Kim, Y.1
Gebara, G.2
Freiler, M.3
Barnett, J.4
Riley, D.5
Chen, J.6
Torres, K.7
Lim, J.E.8
Foran, B.9
Shaapur, F.10
Agarwal, A.11
Lysaght, P.12
Brown, G.A.13
Young, C.14
Borthakur, S.15
Li, H.-J.16
Nguyen, B.17
Zeitzoff, P.18
Bersuker, G.19
Derro, D.20
Bergmann, R.21
Murto, R.W.22
Hou, A.23
Huff, H.R.24
Shero, E.25
Pomarede, C.26
Givens, M.27
Mazanec, M.28
Werkhoven, C.29
more..
-
11
-
-
0033312228
-
2 gate dielectric deposited directly on Si
-
Dec.
-
2 gate dielectric deposited directly on Si," in IEDM Tech. Dig., Dec. 1999, pp. 145-148.
-
(1999)
IEDM Tech. Dig.
, pp. 145-148
-
-
Qi, W.-J.1
Nieh, R.2
Lee, B.H.3
Kang, L.4
Jeon, Y.5
Onishi, K.6
Ngai, T.7
Banerjee, S.8
Lee, J.C.9
-
12
-
-
36449003275
-
Dielectric polarizabilities of ions in oxides and fluorides
-
R. D. Shannon, "Dielectric polarizabilities of ions in oxides and fluorides," J. Appl. Phys., vol. 73, no. 1, pp. 348-366, 1993.
-
(1993)
J. Appl. Phys.
, vol.73
, Issue.1
, pp. 348-366
-
-
Shannon, R.D.1
-
13
-
-
0033882815
-
Electrical conduction and dielectric breakdown in aluminum oxide insulators on silicon
-
Jan.
-
J. Kolodzey, E. A. Chowdhury, T. N. Adam, G. Qui, I. Rau, J. O. Olowolafe, J. S. Suehle, and Y. Chen, "Electrical conduction and dielectric breakdown in aluminum oxide insulators on silicon," IEEE Trans. Electron Devices, vol. 47, pp. 121-128, Jan. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, pp. 121-128
-
-
Kolodzey, J.1
Chowdhury, E.A.2
Adam, T.N.3
Qui, G.4
Rau, I.5
Olowolafe, J.O.6
Suehle, J.S.7
Chen, Y.8
-
14
-
-
84907889526
-
Capacitance degradation due to fringing fields in deep sub-micron MOSFETs with high-k gate dielectrics
-
A. Inani, V. R. Rao, B. Cheng, P. Zeitzoff, and J. C. S. Woo, "Capacitance degradation due to fringing fields in deep sub-micron MOSFETs with high-k gate dielectrics," in Proc. Eur. Solid State Device Research Conf., 1999, pp. 160-163.
-
Proc. Eur. Solid State Device Research Conf., 1999
, pp. 160-163
-
-
Inani, A.1
Rao, V.R.2
Cheng, B.3
Zeitzoff, P.4
Woo, J.C.S.5
-
15
-
-
0036051392
-
Femto-second CMOS technology with high-k offset spacer and SiN gate dielectric with oxygen-enriched interface
-
K. Tsuchiya, K. Ohnishi, M. Horiuchi, S. Tsujikawa, Y. Shimamoto, N. Inada, J. Yugami, F. Ootsuka, and T. Onai, "Femto-second CMOS technology with high-k offset spacer and SiN gate dielectric with oxygen-enriched interface," in VLSI Symp. Tech. Dig., 2002, pp. 150-151.
-
VLSI Symp. Tech. Dig., 2002
, pp. 150-151
-
-
Tsuchiya, K.1
Ohnishi, K.2
Horiuchi, M.3
Tsujikawa, S.4
Shimamoto, Y.5
Inada, N.6
Yugami, J.7
Ootsuka, F.8
Onai, T.9
-
16
-
-
0032072440
-
Fringing-induced barrier lowering (FIBL) in sub-100 nm MOSFETs with high-k gate dielectrics
-
G. C.-F. Yeap, S. Krishnan, and M.-R. Lin, "Fringing-induced barrier lowering (FIBL) in sub-100 nm MOSFETs with high-k gate dielectrics," IEE Electron. Lett., vol. 34, no. 11, pp. 1150-1152, 1998.
-
(1998)
IEE Electron. Lett.
, vol.34
, Issue.11
, pp. 1150-1152
-
-
Yeap, G.C.-F.1
Krishnan, S.2
Lin, M.-R.3
-
17
-
-
0033361786
-
Source-side barrier effects with very high-k dielectrics in 50 nm Si MOSFETs
-
D. L. Kencke, W. Chen, H. Wang, S. Mudanai, Q. Ouyang, A. Tasch, and S. K. Banerjee, "Source-side barrier effects with very high-k dielectrics in 50 nm Si MOSFETs," in Tech. Dig. Device Research Conf., 1999, pp. 22-23.
-
Tech. Dig. Device Research Conf., 1999
, pp. 22-23
-
-
Kencke, D.L.1
Chen, W.2
Wang, H.3
Mudanai, S.4
Ouyang, Q.5
Tasch, A.6
Banerjee, S.K.7
-
18
-
-
0032655915
-
The impact of high-k gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs
-
July
-
B. Cheng, M. Cao, R. Rao, A. Inani, P. V. Voorde, W. M. Greene, J. M. C. Stork, Z. Yu, P. M. Zeitzoff, and J. C. S. Woo, "The impact of high-k Gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs," IEEE Trans. Electron Devices, vol. 46, pp. 1537-1544, July 1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, pp. 1537-1544
-
-
Cheng, B.1
Cao, M.2
Rao, R.3
Inani, A.4
Voorde, P.V.5
Greene, W.M.6
Stork, J.M.C.7
Yu, Z.8
Zeitzoff, P.M.9
Woo, J.C.S.10
-
19
-
-
5444224669
-
Influences of elevated extension structure on the performance of MISFETs with high-k gate dielectrics
-
Y. Kamata, M. Ono, and A. Nishiyama, "Influences of elevated extension structure on the performance of MISFETs with high-k gate dielectrics," in Ext. Abs. Int. Workshop on Gate Insulator IWGI, 2001, pp. 206-209.
-
Ext. Abs. Int. Workshop on Gate Insulator IWGI, 2001
, pp. 206-209
-
-
Kamata, Y.1
Ono, M.2
Nishiyama, A.3
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