A low-power 20-Gb/s CMOS 2:1 multiplexer/driver

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 231-234

  Vadipour, Morteza ^a   Savoj, Jafar ^a  

^a Transpectrum Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

2:1 MULTIPLEXERS; CAPACITIVE PEAKING; CMOS TECHNOLOGY; CURRENT STEERING; HIGH-SPEED DRIVERS; LOW POWER; PEAK-TO-PEAK JITTER;

CMOS INTEGRATED CIRCUITS;

EID: 0742302150     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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3. T. Otsuji, et al., "An 80-Gb/s Multiplexer IC Using In-AlAs/InGaAs/InP HEMT's", IEEE J. Solid-State Circuits, Vol. 33, No. 9, Sept. 1998, pp. 1321-7.
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5. H.-M. Rein, M. Moller, "Design Considerations for Very-High-Speed Si-Bipolar IC's Operating up to 50 Gb/s", IEEE J. Solid-State Circuits, Vol. 31, No. 8, Aug. 1996, pp. 1076-90.
6. J. Savoj, B. Razavi, "A CMOS Interface Circuit for Detection of 1.2-Gb/s RZ Data", Proc. IEEE ISSCC, Feb. 1999, pp. 278-9.
7. Lee, T. H., The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, Cambridge, U.K., 1998.