50 Gbit/s 2:1 multiplexer in 0.13 μm CMOS technology

Electronics Letters

Volumn 40, Issue 2, 2004, Pages 100-101

  Kehrer, D ^a   Wohlmuth, H D ^a   Wurzer, M ^a   Knapp, H ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CAPACITANCE; DATA COMMUNICATION SYSTEMS; ELECTRIC CLOCKS; ELECTRIC CURRENTS; ELECTRIC POWER SUPPLIES TO APPARATUS; FORMAL LOGIC; INDUCTANCE; MOSFET DEVICES; MULTIPLEXING EQUIPMENT; RESISTORS; SWITCHING;

CURRENT-MODE LOGIC (CML); PARASITIC CAPACITANCE;

CMOS INTEGRATED CIRCUITS;

EID: 0742287129     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20040090     Document Type: Article

References (4)

1. Knapp, H., Wohlmuth, H.D., Wurzer, M., and Rest, M.: '25 GHz static frequency divider and 25 Gb/s multiplexer in 0.12 μm CMOS'. IEEE Int. Solid-State Circuits Conf., 2002, pp. 302-303
2. Vadipour, M., and Sayoj, J.: 'A low-power 20-Gb/s 2:1 multiplexer/driver'. European Solid-State Circuit Conf., Firenze, Italy, 2002, pp. 231-234
3. Kehrer, D., Wohlmuth, H.D., Knapp, H., Wurzer, M., and Scholtz, A.L.: '40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120 nm standard CMOS', IEEE J. Solid-State Circuits, 2003, 38, (11), pp. 1830-1837
4. Wohlmuth, H.D., and Kehrer, D.: 'A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS'. European Solid-State Circuits Conf., Firenze, Italy, 2002, pp. 823-826