GigaOp DSP on FPGA

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 36, Issue 1, 2004, Pages 41-55

  Hutchings, Brad L ^a   Nelson, Brent E ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

DSP; FPGA

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; COMPUTATIONAL COMPLEXITY; COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS; FREQUENCY MULTIPLYING CIRCUITS; MICROPROCESSOR CHIPS; OPTIMIZATION; RADAR TARGET RECOGNITION; SONAR;

AUTOMATED TARGET RECOGNITION; PROGRAMMABLE PROCESSORS;

DIGITAL SIGNAL PROCESSING;

EID: 0742286210     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1023/B:VLSI.0000008069.78914.5e     Document Type: Conference Paper

References (23)

1. C. Dick, "Computing the Discrete Fourier Transform on FPGA Based Systolic Arrays," in ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, Feb. 1996, pp. 129-135.
2. W. Culbertson, R. Amerson, R. Carter, P. Kuekes, and G. Snider, "Exploring Architectures for Volume Visualization on the Teramac Custom Computer," in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, K. Pocek and J. Arnold (Eds.), Napa, CA: IEEE Computer Society Press, April 1996, pp. 80-88.
3. R.J. Petersen, "An Assessment of the Suitability of Reconfigurable Systems for Digital Signal Processing," M.S. Thesis, Brigham Young University, 1995, p. 60.
4. L.E. Turner, P.J.W. Graumann, and S.G. Gibb, "Bit-Serial FIR Filters with CSD Coefficients for FPGAs," in Field-Programmable Logic and Applications. 5th International Workshop on Field-Programmable Logic and Applications, W. Moore and W. Luk (Eds.), Oxford, UK: Springer-Verlag, Sept. 1995, pp. 311-320.
5. J.E. Vuillemin, "On Computing Power," in Programming Languages and System Architectures, J. Gutknecht (Ed.), vol. 782 of Lecture Notes in Computer Science, Springer-Verlag, 1994, pp. 69-86.
6. R. Hudson, D. Lehn, and P. Athanas, "A Run-Time Reconfigurable Engine for Image Interpolation," in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '98), K.L. Pocek and J.M. Arnold (Eds.), IEEE Computer Society Press, April 1998, pp. 88-95.
7. A. Dandalis and V.K. Prasanna, "Fast Parallel Implementation of DFT Using Configurable Devices," in Field-Programmable Logic: Smart Applications, New Paradigms, and Compilers. 6th International Workshop on Field-Programmable Logic and Applications, M. Glesner, W. Luk, and P.Y.K. Cheung (Eds.), London, UK: Springer-Verlag, Sept. 1997, pp. 314-323.
8. W.E. King, T.H. Drayer, R.W. Conners, and P. Araman, "Using MORPH in an Industrial Machine Vision System," in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, K.L. Pocek and J. Arnold (Eds.), Napa, CA, April 1996, pp. 18-26.
9. G. Panneerselvam, P.J.W. Graumann, and L.E. Turner. "Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs," in Field-Programmable Logic and Applications. 5th International Workshop on Field-Programmable Logic and Applications, W. Moore and W. Luk (Eds.), Oxford, UK: Springer-Verlag, Sept. 1995, pp. 272-281.
10. C.H. Dick and F. Harris, "FIR Filtering with FPGAs Using Quadrature Sigma-Delta Modulation Encoding," in Field-Programmable Logic: Smart Applications, New Paradigms, and Compilers. 6th International Workshop on Field-Programmable Logic and Applications, R.W. Hartenstein and M. Glesner (Eds.), Darmstadt, Germany: Springer-Verlag, Sept. 1996, pp. 361-365.
11. N. Shirazi, P.M. Athanas, and A.L. Abbott, "Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine," in Field-Programmable Logic and Applications. 5th International Workshop on Field-Programmable Logic and Applications, W. Moore and W. Luk (Eds.), Oxford, UK: Springer-Verlag. Sept. 1995, pp. 282-292.
12. T. Moeller and D. Martinez, "Field Programmable Gate Array Based Radar Front-End Digital Signal Processing," in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '99). K.L. Pocek and J.M. Arnold (Eds.), IEEE Computer Society Press, April 1999, pp. 178-187.
13. R. Tessier and W. Burleson. "Reconfigurable Computing and Digital Signal Processing: A Survey," Journal of VLSI Signal Processing, May 2001, pp. 7-27.
14. B. Nelson, "Configurable Computing and SONAR Processing - Architectures and Implementations," in ASILOMAR 2001, Nov. 2001.
15. B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting, "A CAD Suite for High-Performance FPGA Design," in Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, K.L. Pocek and J.M. Arnold (Eds.), Napa, CA: IEEE Computer Society Press, April 1999, pp. 12-24.
16. ERIM (Environmental Research Institute of Michigan), C4PL Advanced Programming Manual, 3rd edition. Ann Arbor, Michigan, Feb. 1993.
17. B.L. Hutchings and K.S. Hemmert, "An Application Specific Compiler for High Speed Binary Image Morphology," in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '01), K.L. Pocek and J.M. Arnold (Eds.), IEEE Computer Society Press, April 2001.
18. M. Sonka, V. Hlavac, and R. Boyle, Image Processing, Analysis, and Machine Vision. PWS Publishing, 1999.
19. S. Scalera, M. Falco, and B. Nelson, "A Reconfigurable Computing Architecture for Microsensors," in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '00), K.L. Pocek and J.M. Arnold (Eds.). IEEE Computer Society Press, April 2000, pp. 59-67.
20. N.L. Owlsey, Array Signal Processing. Prentice-Hall, 1985.
21. R. Andraka, "A Survey of CORDIC Algorithms for FPGA-Based Computers," in ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, Feb. 1998, pp. 191-200.
22. P.M. Kogge, The Architecture of Pipelined Computers. McGraw-Hill, 1981.
23. A. Tolstoy, Matched Field Processing For Underwater Acoustics. World Scientific, 1993.