A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 1, 2004, Pages 169-183

  Huang, Yuan Hao ^a   Ma, Hsi Pin ^a,b   Liou, Ming Luen ^a,c   Chiueh, Tzi Dar ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^c MEDIATEK INC   (Taiwan)

Author keywords

Digital signal processor (DSP); Sub word parallelism; Wireless communication

Indexed keywords

CMOS INTEGRATED CIRCUITS; CODE DIVISION MULTIPLE ACCESS; COMPUTATIONAL COMPLEXITY; INTEGRATED CIRCUIT MANUFACTURE; LOCAL AREA NETWORKS; MICROPROCESSOR CHIPS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; TELECOMMUNICATION LINKS; TRANSCEIVERS; WIRELESS TELECOMMUNICATION SYSTEMS;

MULTIPLICATION AND ACCUMULATION; SUB-WORD PARALLELISM; WIDEBAND CODE DIVISION MULTIPLE ACCESS;

DIGITAL SIGNAL PROCESSING;

EID: 0742268978     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.820861     Document Type: Article

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