Testability-Driven Random Test-Pattern Generation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 6, Issue 6, 1987, Pages 1082-1087

  Lisanke, Robert ^a   Brglez, Franc ^b   Degeus, Aart J ^c   Gregory, David ^c  

^a MCNC   (United States)

^b BNR   (United States)

^c Optimal Solutions Inc ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0348022769     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1987.1270348     Document Type: Article

References (14)

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11. F. Brglez, P. Pownall, and R. Hum, “Accelerated ATPG and fault grading via testability analysis,” in Proc. 1985 IEEE Int. Symp. Circuits Syst., June 1985, pp. 695–698.
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