-
1
-
-
0024104573
-
Cache Performance of Operating Systems and Multiprogramming
-
Nov.
-
A. Agarwal, J. Hennessy, and M. Horowitz, "Cache Performance of Operating Systems and Multiprogramming," ACM Trans. Computer Systems, Vol. 6(4), Nov. 1988, pp. 393-431.
-
(1988)
ACM Trans. Computer Systems
, vol.6
, Issue.4
, pp. 393-431
-
-
Agarwal, A.1
Hennessy, J.2
Horowitz, M.3
-
2
-
-
0027192667
-
Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches
-
San Diego, CA, May
-
A. Agarwal, and S. Pudar, "Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches," Proc. 20th Int'l Symp. Comp. Arch., San Diego, CA, May 1993, pp. 179-190.
-
(1993)
Proc. 20th Int'l Symp. Comp. Arch.
, pp. 179-190
-
-
Agarwal, A.1
Pudar, S.2
-
3
-
-
0029710803
-
Predictive Sequential Associative Cache
-
San Jose, CA, Jan.
-
B. Calder, D. Grunwald, and J. Emer, "Predictive Sequential Associative Cache," Proc. 2nd Symp. High-Performance Comp. Arch., San Jose, CA, Jan. 1996, pp. 244-253.
-
(1996)
Proc. 2nd Symp. High-Performance Comp. Arch.
, pp. 244-253
-
-
Calder, B.1
Grunwald, D.2
Emer, J.3
-
4
-
-
0023252545
-
Cache Design of a Sub-Micron CMOS System/370
-
Pittsburgh, PA, June
-
J. Chang, H. Chao, and K. So, "Cache Design of A Sub-Micron CMOS System/370," Proc. 14th Int'l Symp. Comp. Arch., Pittsburgh, PA, June 1987, pp. 208-213.
-
(1987)
Proc. 14th Int'l Symp. Comp. Arch.
, pp. 208-213
-
-
Chang, J.1
Chao, H.2
So, K.3
-
5
-
-
0347150682
-
LRU-Based Column Associative Caches
-
May
-
B. Chung, and J. Peir, "LRU-Based Column Associative Caches," Comp. Arch. News, Vol. 26(2) May 1998, pp. 9-17.
-
(1998)
Comp. Arch. News
, vol.26
, Issue.2
, pp. 9-17
-
-
Chung, B.1
Peir, J.2
-
6
-
-
0030722782
-
Eliminating Cache Conflict Misses Through XOR-Based Placement Functions
-
Vienna, Austria
-
A. Gonzalez, M. Valero, N. Topham and J.M. Parcerisa, "Eliminating Cache Conflict Misses Through XOR-Based Placement Functions," Proc. 11th Int'l Conference Supercomputing, Vienna, Austria, 1997, pp. 76-83.
-
(1997)
Proc. 11th Int'l Conference Supercomputing
, pp. 76-83
-
-
Gonzalez, A.1
Valero, M.2
Topham, N.3
Parcerisa, J.M.4
-
7
-
-
0024173488
-
A Case for Direct-Mapped Caches
-
Dec.
-
M. Hill "A Case for Direct-Mapped Caches," IEEE Computer, Vol. 21(12), Dec. 1988, pp. 25-40.
-
(1988)
IEEE Computer
, vol.21
, Issue.12
, pp. 25-40
-
-
Hill, M.1
-
8
-
-
0030717768
-
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
-
Denver, CO, Jun.
-
T. Johnson, and W. Hwu, "Run-Time Adaptive Cache Hierarchy Management via Reference Analysis," Proc. 24th Int'l Symp. Comp. Arch., Denver, CO, Jun. 1997, pp. 315-326.
-
(1997)
Proc. 24th Int'l Symp. Comp. Arch.
, pp. 315-326
-
-
Johnson, T.1
Hwu, W.2
-
9
-
-
0030677583
-
Prefetching using Markov Predictors
-
Denver, CO, Jun
-
D. Joseph, and D. Grunwald, "Prefetching using Markov Predictors," Proc. 24th Int'l Symp. Comp. Arch., Denver, CO, Jun 1997, pp. 252-263.
-
(1997)
Proc. 24th Int'l Symp. Comp. Arch.
, pp. 252-263
-
-
Joseph, D.1
Grunwald, D.2
-
10
-
-
0025429331
-
Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers
-
Seattle, WA, May
-
N. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of A Small Fully-Associative Cache and Prefetch Buffers," Proc. 17th Int'l Symp. Comp. Arch., Seattle, WA, May 1990, pp. 364-373.
-
(1990)
Proc. 17th Int'l Symp. Comp. Arch.
, pp. 364-373
-
-
Jouppi, N.1
-
11
-
-
0028201665
-
Tradeoffs in Two-Level On-Chip Caching
-
Chicago, IL, April
-
N. Jouppi and S. Wilton "Tradeoffs in Two-Level On-Chip Caching," Proc. 21st Int'l Symp. Comp. Arch., Chicago, IL, April 1994, pp. 34-45.
-
(1994)
Proc. 21st Int'l Symp. Comp. Arch.
, pp. 34-45
-
-
Jouppi, N.1
Wilton, S.2
-
12
-
-
0029666649
-
The Difference-bit Cache
-
Philadelphia, PA, May
-
T. Juan, T. Lang, and J. Navarro, "The Difference-bit Cache," Proc. 23rd Int'l Symp. Comp. Arch., Philadelphia, PA, May 1996, pp. 114-120.
-
(1996)
Proc. 23rd Int'l Symp. Comp. Arch.
, pp. 114-120
-
-
Juan, T.1
Lang, T.2
Navarro, J.3
-
13
-
-
0008574019
-
PA7200: A PA-RISC Processor with Integrated High Performance MP Bus Interface
-
San Francisco, CA, Feb.
-
G. Kurpanek, et. al, "PA7200: A PA-RISC Processor with Integrated High Performance MP Bus Interface," COMPCON Digest of Papers, San Francisco, CA, Feb. 1994, pp. 375-382.
-
(1994)
COMPCON Digest of Papers
, pp. 375-382
-
-
Kurpanek, G.1
-
14
-
-
84944785783
-
Cache Design with Partial Address Matching
-
San Jose, CA, Dec.
-
L. Liu "Cache Design with Partial Address Matching," MICRO'27, San Jose, CA, Dec. 1994, pp. 128-136.
-
(1994)
MICRO'27
, pp. 128-136
-
-
Liu, L.1
-
16
-
-
0028294834
-
Evaluating Stream Buffers as a Secondary Cache Replacement
-
Chicago, IL, April
-
S. Palacharla, and R. Kessler, "Evaluating Stream Buffers as a Secondary Cache Replacement," Proc. 16th Int'l Symp. Comp. Arch., Chicago, IL, April 1994, pp. 24-33.
-
(1994)
Proc. 16th Int'l Symp. Comp. Arch.
, pp. 24-33
-
-
Palacharla, S.1
Kessler, R.2
-
17
-
-
0030264304
-
Improving Cache Performance with Balanced Tag and Data Paths
-
Cambridge, MA, Oct.
-
J. Peir, W. Hsu, H. Young, and S. Ong, "Improving Cache Performance with Balanced Tag and Data Paths," Proc. 7th Int'l Conf. Architectural Support for Programming Languages and Operating Systems, Cambridge, MA, Oct. 1996, pp. 268-278.
-
(1996)
Proc. 7th Int'l Conf. Architectural Support for Programming Languages and Operating Systems
, pp. 268-278
-
-
Peir, J.1
Hsu, W.2
Young, H.3
Ong, S.4
-
19
-
-
84948125832
-
Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design
-
Ithaca, NY, Aug.
-
J. Rivers, and E. Davidson, "Reducing Conflicts in Direct-Mapped Caches with A Temporality-Based Design," Proc. 1996 Int'l Conf. Parallel Processing, Ithaca, NY, Aug. 1996, pp. 151-162.
-
(1996)
Proc. 1996 Int'l Conf. Parallel Processing
, pp. 151-162
-
-
Rivers, J.1
Davidson, E.2
-
20
-
-
0027307814
-
A Case for Two-Way Skewed-Associative Caches
-
San Diego, CA, May
-
A. Seznec, "A Case for Two-Way Skewed-Associative Caches," Proc. 20th Int'l Symp. Comp. Arch., San Diego, CA, May 1993, pp. 169-178.
-
(1993)
Proc. 20th Int'l Symp. Comp. Arch.
, pp. 169-178
-
-
Seznec, A.1
-
21
-
-
0002729410
-
DASC Cache
-
Raleigh, NC, Jan.
-
A. Seznec, "DASC Cache," Proc. 1st Symp. High-Performance Comp. Arch., Raleigh, NC, Jan. 1995, pp. 134-143.
-
(1995)
Proc. 1st Symp. High-Performance Comp. Arch.
, pp. 134-143
-
-
Seznec, A.1
-
22
-
-
0018106484
-
Sequential Program Prefetching in Memory Hierarchies
-
Dec.
-
A. Smith, "Sequential Program Prefetching in Memory Hierarchies," IEEE Computer, Vol. 11(12), Dec. 1978, pp. 7-21.
-
(1978)
IEEE Computer
, vol.11
, Issue.12
, pp. 7-21
-
-
Smith, A.1
-
23
-
-
0020177251
-
Cache Memories
-
Sep.
-
A. Smith, "Cache Memories," Computing Surveys, Vol. 14(3), Sep. 1982, pp. 473-530.
-
(1982)
Computing Surveys
, vol.14
, Issue.3
, pp. 473-530
-
-
Smith, A.1
-
24
-
-
0024034266
-
Cache Operations by MRU Change
-
Jun.
-
K. So and R. Rechtschaffen, "Cache Operations by MRU Change," IEEE Trans. Computers, Vol. 37(6), Jun. 1988, pp. 700-709.
-
(1988)
IEEE Trans. Computers
, vol.37
, Issue.6
, pp. 700-709
-
-
So, K.1
Rechtschaffen, R.2
-
26
-
-
0347255406
-
-
Revision C, April
-
Sun Microsystems, "Introduction to Shade," Revision C, April 1993.
-
(1993)
Introduction to Shade
-
-
-
28
-
-
0031232542
-
Two Fast and High-Associativity Cache Schemes
-
Sep/Oct
-
C. Zhang, X. Zhang, and Y. Yan, "Two Fast and High-Associativity Cache Schemes," IEEE Micro, Vol. 17(5), Sep/Oct 1997, pp. 40-49.
-
(1997)
IEEE Micro
, vol.17
, Issue.5
, pp. 40-49
-
-
Zhang, C.1
Zhang, X.2
Yan, Y.3
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