Systolic and scalable architectures for digit-serial multiplication in fields GF(pm)

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2904, Issue , 2003, Pages 349-362

  Bertoni, Guido ^a   Guajardo, Jorge ^b   Orlando, Gerardo ^c  

^a POLITECNICO DI MILANO   (Italy)

^b INFINEON TECHNOLOGIES AG   (Germany)

^c GENERAL DYNAMICS ADVANCED INFORMATION SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRYPTOGRAPHY; MULTIPLYING CIRCUITS; PUBLIC KEY CRYPTOGRAPHY;

CRYPTOGRAPHIC APPLICATIONS; DIGIT-SERIAL; FPGA IMPLEMENTATIONS; GROUND FIELD; SCALABLE ARCHITECTURES; SIGNATURE SCHEME; TATE PAIRING; TOWER FIELDS;

ARCHITECTURE;

EID: 0347526077     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-24582-7_26     Document Type: Article

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