Aliasing error for a mask ROM built-in self-test

IEEE Transactions on Computers

Volumn 45, Issue 3, 1996, Pages 270-277

  Iwasaki, Kazuhiko ^a,b   Nakamura, Shigeo ^c  

^a IEEE

^b TOKYO METROPOLITAN UNIVERSITY   (Japan)

^c CHIBA UNIVERSITY   (Japan)

Author keywords

Aliasing probability; Built in self test; Experimental faults analysis; Mask ROM; MISRs

Indexed keywords

EID: 0347250154     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.485566     Document Type: Article

References (27)

1. H. Fujiwara, Logic Testing and Design for Testability. MIT Press, 1985.
2. P. Bardell, W. McAnney, and J. Savir, Built-In Self-Test for VLSI. John Wiley, 1987.
3. J. Broseghini and D.H. Lenhert, "An ALU-Based Programmable MISR/Pseudorandom Generator for a MC68HC11 Family Self-Test," Int'l Test Conf., pp. 349-358, Oct. 1993.
4. R. Patel and K. Yarlagadda, "Testability Features of the Super-SPARC Microprocessor," Int'l Test Conf., pp. 773-781, Oct. 1993.
5. P. Bardell and M.J. Lapointe, "Production Experience with Built-In Self-Test in the IBM ES/9000 System," Int'l Test Conf., pp. 28-36, Oct. 1991.
6. C.E. Stroud, "Built-in Self-Test for High-Speed Data-Path Circuitry," Int'l Test Conf., pp. 47-56, Oct. 1991.
7. N. Jarwala and C.W. Yau, "Achieving Board-Level BIST Using the Boundary Scan Master," Int'l Test Conf., pp. 649-664, Oct. 1991.
8. M.G. Karpovsky and S.M. Chaudhry, "Design of Self-Diagnostic Boards by Multiple Signature Analysis," IEEE Trans. Computers, vol. 42, no. 9, Sept. 1993.
9. H. Maeno, K. Nii, S. Sakayanagi, and S. Kato, "LSSD Compatible and Concurrently Testable RAM," Int'l Test Conf., pp. 608-614, Sept. 1992.
10. J. Sas, G.V. Wauwe, E. Huyskens, and D. Rabaey, "BIST for Embedded RAMs with Coverage Calculation," Int'l Test Conf., pp. 339-358, Oct. 1993.
11. P. Camurati, P. Prinetto, M.S. Peorda, S. Barbagallo, A. Burri, and D. Medina, "An Industrial Experience in the Built-In Self Test of Embedded RAMs," VLSI Test Symp., pp. 306-311, Apr. 1994.
12. Y. Zorian and A. Ivanov, "EEODM: An Effective BIST Scheme for ROMs," Int'l Test Conf., pp. 871-879, 1990.
13. P. Nagvajara and M.G. Karpovsky, "Built-In Self-Diagnostic Read-Only-Memories," Int'l Test Conf., pp. 695-703, Oct. 1991.
14. K. Iwasaki, T. Fujiwara, and T. Kasami, "A Defect-Tolerant Design for Mask ROMs," IEEE VLSI Test Symp., pp. 171-175, Apr. 1992.
15. T.W. Williams, W. Daehn, M. Gruetzner, and C.W. Starke, "Bounds and Analysis of Aliasing Errors in Linear Feedback Shift Registers," IEEE Trans. Compter-Aided Design/ICAS, vol. 7, no. 1, pp. 75-83, Jan. 1988.
16. K. Iwasaki, "Analysis and Proposal of Signature Circuits for LSI Testing," IEEE Trans. Computer-Aided Design/ICAS, vol. 7, no. 1, pp. 84-90, Jan. 1988.
17. m-ary Symmetric Channel," IEEE Trans. Computer-Aided Design/ICAS, vol. 9, no. 4, pp. 427-438, Apr. 1990.
18. D.K. Pradhan, S.K. Gupta, and M.G. Karpovsky, "Aliasing Probability for Multiple-Input Signature Analyzer and a New Compression Technique," IEEE Trans. Computers, vol. 39, no. 4, pp. 586-591, Apr. 1990.
19. D.K. Pradhan and S.K. Gupta, "A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression," IEEE Trans. Computers, vol. 40, no. 6, pp. 743-763, June 1991.
20. K. Iwasaki and N. Yamaguchi, "Design of Signature Circuits Based on Weight Distribution of Error-Correcting Codes," Int'l Test Conf., pp. 779-785, Sept. 1990.
21. N.R. Saxena, P. Franco, and E.J. McCluskey, "Simple Bounds on Serial Signature Analysis Aliasing for Random Testing," IEEE Trans. Computers, vol. 41, no. 5, pp. 638-645, May 1992.
22. K. Iwasaki, S. Feng, T. Fujiwara and T. Kasami, "Comparison of Aliasing Probability for Multiple MISRs and M-Stage MISRs with m Inputs," IEICE Trans. Information and Systems, vol. E75-D, no. 6, pp. 835-841, Nov. 1992.
23. T. Kameda, S. Pilarski, and A. Ivanov, "Notes on Multiple Input Signature Analysis," IEEE Trans. Computers, vol. 42, no. 2, pp. 228-234, Feb. 1993.
24. G. Edirisooriya and J.P. Robinson, "Time and Space Correlated Errors in Signature Analysis," IEEE VLSI Test Symp., pp. 275-281, Apr. 1993.
25. S. Feng, T. Fujiwara, T. Kasami, and K. Iwasaki, "On the Maximum Value of Aliasing Probabilities for Single Input Signature Registers," IEEE VLSI Test Symp., pp. 267-274, Apr. 1993.
26. C.H. Stapper, "Improved Yield Models for Fault-Tolerant Memory Chips," IEEE Trans. Computers, vol. 42, no. 7, pp. 872-881, July 1993.
27. S. Lin and D.J. Costello Jr., Error Control Coding. Prentice Hall, 1983.