Efficient design of binary to RNS converters

Journal of Circuits, Systems and Computers

Volumn 9, Issue 3-4, 1999, Pages 145-154

  Mohan, P V Ananda ^a  

^a Transmission R and D ItI Limited   (India)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0347038174     PISSN: 02181266     EISSN: None     Source Type: Journal    
DOI: 10.1142/s021812669900013x     Document Type: Article

References (13)

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3. S. J. Piestrak, "Design of residue generators and multioperand modulo adders using carry-save adders", Proc. 10th Symp. Computer Arithmetic, France, 1991, pp. 100-107.
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9. A. B. Premkumar, "An RNS to binary converter in (2n-1), 2n, (2n+1) modul set", IEEE Trans. Circuits Syst.-II 39 (1992) 480-482.
10. A. B. Premkumar, "An RNS to binary converter in a three moduli set with common factors", IEEE Trans. Circuits Syst.-II 42 (1995) 298-301.
11. M. A. Bayoumi, G. A. Jullien and W. C. Miller, "A VLSI implementation of residue adders", IEEE Trans. Circuits Syst. 34 (1987) 284-288.
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13. K. M. Elleithy and M. A. Bayoumi, "A⊖(1) algorithm for modulo addition", IEEE Trans. Circuits Syst. CAS-37 (1990) 628-631.