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Volumn 44, Issue 16, 1999, Pages 103-114

Figuring out reconfigurable logic

(1) Dipert, Brian a

a NONE

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0346727633 PISSN: 00127515 EISSN: None Source Type: Trade Journal
DOI: None Document Type: Article

Times cited : (3)

References (8)

1
- 0347406919
- Innovation ignores economy: The 1999 ISSCC
- March 18
- Dipert, Brian, "Innovation ignores economy: the 1999 ISSCC," EDN, March 18, 1999, Pg 11.
- (1999) EDN , pp. 11
- Dipert, B.¹

2
- 0346797653
- Focusing on chip programming
- Jan 7
- Dipert, Brian, "Focusing on chip programming," EDN, Jan 7, 1999, pg 58.
- (1999) EDN , pp. 58
- Dipert, B.¹

3
- 0346776455
- Logic that mutates while-u-wait
- Nov 7
- Maxfield, Clive, "Logic that mutates while-u-wait," EDN, Nov 7, 1996, pg 137.
- (1996) EDN , pp. 137
- Maxfield, C.¹

4
- 0030568684
- Fast and flexible: FIR filters in reconfigurable logic
- July 4
- Conner, Doug, "Fast and flexible: FIR filters in reconfigurable logic," EDN, July 4, 1996, pg 65.
- (1996) EDN , pp. 65
- Conner, D.¹

5
- 3042944557
- Reconfigurable logic: Built-in adaptability
- June 20
- Conner, Doug, "Reconfigurable logic: built-in adaptability," EDN, June 20, 1996, pg 42.
- (1996) EDN , pp. 42
- Conner, D.¹

6
- 0346776457
- DSP design tools target FPGAs
- June 20
- Levy, Markus, "DSP design tools target FPGAs," EDN, June 20, 1996, pg 75.
- (1996) EDN , pp. 75
- Levy, M.¹

7
- 0030106028
- Reconfigurable logic: Hardware speed with software flexibility
- March 28
- Conner, Doug, "Reconfigurable logic: hardware speed with software flexibility," EDN, March 28, 1996, pg 52.
- (1996) EDN , pp. 52
- Conner, D.¹

8
- 0346776460
- Application note Atrnel Corp
- Application note "Implementing Cache Logic with FPGAs," Atrnel Corp, 1997.
- (1997) Implementing Cache Logic with FPGAs

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.