System Level Design and Verification Using a Synchronous Language

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 433-439

  Berry, Gérard ^a   Kishinevsky, Michael ^b   Singh, Satnam ^c  

^a ANSYS Esterel Technologies   (France)

^b INTEL CORPORATION   (United States)

^c XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

C (PROGRAMMING LANGUAGE); COMPUTER SIMULATION; ERROR ANALYSIS; INTERNET; MATHEMATICAL MODELS; NETWORK PROTOCOLS; PROGRAM COMPILERS;

FINITE STATE MACHINES (FSM); SYNCHRONOUS LANGUAGES;

COMPUTER AIDED DESIGN;

EID: 0346148457     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.2003.159720     Document Type: Conference Paper

References (13)

1. SystemC, 2002, website at http://www.systemc.org.
2. UCI, SpecC, 2002, website at http://ics.uci.edu/ specc.
3. G. Berry, "The Foundations of Esterel," in Proof, Language and Interaction: Essays in Honour of Robin Milner, ser. Foundations of Computing Series, G. Plotkin, C. Stirling, and M. Tofte, Eds. MIT Press, Aug. 2000.
4. C. André, "Representation and analysis of reactive behaviors: A synchronous approach," in Proc. CESA'96, Lille, France, July 1996.
5. G. Berry, The Esterel v5_91 Primer. Draft book, available at http://www.esterel-technologies.com, version 3, August 2000.
6. Esterel Studio 5.0 reference manual, Esterel Technologies, 2003.
7. G. Berry and M. Kishinevsky, "Hardware Esterel language extension proposal," Tech. Rep., August 2000, available at http://www.esterel-technologies.com.
8. K. Schneider, "Embedding imperative synchronous languages in interactive theorem provers," in Proc. Int. Conference Application of Concurrency in System Design, June 2001.
9. Virtex™-II Platform FPGA Handbook, Xilinx Inc., December 2000.
10. Xilinx, Aurora Technology Overview, 2003.
11. CoWare, 2003, website at http://www.coware.com.
12. S. Singh, "Design and verification of CoreConnect™ IP using Esterel," the 12th Advanced Research Working Conference on Correct Hardware Design and Verification Methods, L'Aquila, Italy, 2003.
13. IBM, The CoreConnect™ Bus Architecture, 1999.