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Volumn , Issue , 2003, Pages 741-746

Frosty: A Fast Hierarchy Extractor for Industrial CMOS Circuits

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL CONNECTED COMPONENTS (CCC); CIRCUIT GRAPHS; STRUCTURAL RECOGNITION;

EID: 0346148445     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (13)

References (10)
  • 4
    • 0032320506 scopus 로고    scopus 로고
    • GateMaker: A transistor to gate level model extractor for simulation, automatic test pattern generation and verification
    • S. Kundu, "GateMaker: A transistor to gate level model extractor for simulation, automatic test pattern generation and verification", Proc. of International Test Conference, pp. 372-381, 1998.
    • (1998) Proc. of International Test Conference , pp. 372-381
    • Kundu, S.1
  • 5
    • 0024137454 scopus 로고
    • LOGEX - An automatic logic extractor from transistor to gate level for CMOS technology
    • M. Boehner, "LOGEX - an automatic logic extractor from transistor to gate level for CMOS technology", Proc. IEEE/ACM Design Automation Conference, pp. 517-522, 1988.
    • (1988) Proc. IEEE/ACM Design Automation Conference , pp. 517-522
    • Boehner, M.1
  • 8
    • 0028377204 scopus 로고
    • Pattern matching and refinement hybrid approach to circuit comparison
    • Feb.
    • G. Pelz and U. Roettcher, "Pattern matching and refinement hybrid approach to circuit comparison", IEEE Transactions on Computer-Aided Design, pp. 264-275, vol. 13, no. 2, Feb. 1994.
    • (1994) IEEE Transactions on Computer-aided Design , vol.13 , Issue.2 , pp. 264-275
    • Pelz, G.1    Roettcher, U.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.