Effects of buried layer geometry on characteristics of double polysilicon bipolar transistors

IEEE Electron Device Letters

Volumn 19, Issue 5, 1998, Pages 160-162

  Kenneth, K O ^a,b   Scharf, Brad W ^a,c  

^a IEEE   (United States)

^b University of Florida   (United States)

^c ANALOG DEVICES INC   (United States)

Author keywords

Analog; Bipolar transistors; Buried layer; Bv CEO; Subcollector

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC BREAKDOWN OF SOLIDS; OPTIMIZATION;

BREAKDOWN VOLTAGE; DOUBLE POLYSILICON BIPOLAR TRANSISTORS;

BIPOLAR TRANSISTORS;

EID: 0345902565     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.669735     Document Type: Article

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