On the complexity of negation-limited boolean networks

SIAM Journal on Computing

Volumn 27, Issue 5, 1998, Pages 1334-1347

  Beals, Robert ^a  

^a INSTITUTE FOR ADVANCED STUDY   (United States)

Author keywords

Circuit complexity; Lower bounds; Negation limited circuit; Upper bounds

Indexed keywords

EID: 0345888511     PISSN: 00975397     EISSN: None     Source Type: Journal    
DOI: 10.1137/S0097539794275136     Document Type: Article

References (3)

1. M. AJTAI, J. KOMLÓS, AND E. SZEMERÉDI, An O(n log n) sorting network, in Proc. 15th Annual ACM Symposium on the Theory of Computing, ACM, New York, 1983, pp. 1-9.
2. S. B. AKERS, JR., On maximum inversion with minimum inverters, IEEE Trans. Comput., 17 (1968), pp. 134-135.
3. N. ALON AND R. B. BOPPANA, The monotone circuit complexity of Boolean functions, Combinatorica, 7 (1987), pp. 1-22.