Industry confronts sub-100 nm challenges

Semiconductor International

Volumn 26, Issue 1, 2003, Pages 42-48

  Peters, Laura ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

COPPER PLATING; CUSTOMER SATISFACTION; DIELECTRIC DEVICES; ELECTRIC POTENTIAL; ETCHING; GATES (TRANSISTOR); IMAGING TECHNIQUES; OPTICAL RESOLVING POWER; PHOTORESISTORS; POWER ELECTRONICS; PRODUCTION ENGINEERING; SEMICONDUCTING SILICON; SEMICONDUCTOR MATERIALS; TRANSISTORS;

CHROMELESS PHASE LITHOGRAPHY (CPL); METAL ELECTRODES; RESOLUTION ENHANCEMENT TECHNIQUES (RET); SILICON-ON-INSULATOR (SOI);

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0345617104     PISSN: 01633767     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Review

References (3)

1. A. Hand, "Chromeless Phase Lithography Offers Better RET Performance," Semiconductor International, December 2002, p. 30.
2. A. Braun, "High-k Materials Challenge Deposition, Etch and Metrology," Semiconductor International, November 2002, p. 55.
3. L. Peters, "IMEC Explores Interconnect, Reliability Issues Beyond 65 nm," Semiconductor International, November 2002, p. 19.