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Volumn 1304, Issue , 1997, Pages 245-254

Technology mapping of LUT based FPGAs for delay optimisation

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EID: 0344908183     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-63465-7_229     Document Type: Conference Paper
Times cited : (1)

References (19)
  • 2
    • 0028259317 scopus 로고
    • FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Design
    • Cong, J., Ding, Y.: FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13(1) (1994) 1-12
    • (1994) IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol.13 , Issue.1 , pp. 1-12
    • Cong, J.1    Ding, Y.2
  • 3
    • 33746967767 scopus 로고
    • An Optimal Performance-driven Technology Mapping Algorithm for LUT based FPGAs under arbitrary net-delay models
    • Cong, J., Ding, Y, Chen, K,: An Optimal Performance-driven Technology Mapping Algorithm for LUT based FPGAs under arbitrary net-delay models. Int. Conf. on Computer-Aided Design and Computer Graphics, (1993) 599-604
    • (1993) Int. Conf. on Computer-Aided Design and Computer Graphics , pp. 599-604
    • Cong, J.1    Ding, Y.2    Chen, K.3
  • 4
    • 0027307171 scopus 로고
    • On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping
    • Cong, J., Ding, Y.: On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. 30th Design Automation Conference (DAC), (1993) 213-218
    • (1993) 30Th Design Automation Conference (DAC) , pp. 213-218
    • Cong, J.1    Ding, Y.2
  • 5
    • 0029707981 scopus 로고    scopus 로고
    • Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design
    • Cong, J., Hwang, Y. Y.: Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. 33th Design Automation Conference, (1996) 726-729
    • (1996) 33Th Design Automation Conference , pp. 726-729
    • Cong, J.1    Hwang, Y.Y.2
  • 12
    • 0030110591 scopus 로고    scopus 로고
    • Tradeoff literals against support for Logic Synthesis of LUT based FPGAs
    • Lu, A., Dagless, E., Saul, J.: Tradeoff literals against support for Logic Synthesis of LUT based FPGAs. IEE Proceedings on Computers and Digital Techniques, 143(2) (1996) 111-119
    • (1996) IEE Proceedings on Computers and Digital Techniques , vol.143 , Issue.2 , pp. 111-119
    • Lu, A.1    Dagless, E.2    Saul, J.3
  • 13
    • 0027045290 scopus 로고
    • Sangiovanni-Vincentelli, A.: Performance Directed Synthesis for Table Look Up Programmable Gate Arrays
    • Murgai, R., Shenoy, N., Brayton, R. K., Sangiovanni-Vincentelli, A.: Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. IEEE International Conference on Computer-Aided Design, (1991) 572-575
    • (1991) IEEE International Conference on Computer-Aided Design , pp. 572-575
    • Murgai, R.1    Shenoy, N.2    Brayton, R.K.3
  • 18
    • 0028697847 scopus 로고
    • Maple: A simultaneous technology mapping, placement, and global routing algorithm for Field-Programmable Gate Arrays
    • Togawa, N., Sato, M., Ohtsuki, T.: Maple: A simultaneous technology mapping, placement, and global routing algorithm for Field-Programmable Gate Arrays. IEEE International Conference on Computer-Aided Design, (1994) 156-163
    • (1994) IEEE International Conference on Computer-Aided Design , pp. 156-163
    • Togawa, N.1    Sato, M.2    Ohtsuki, T.3
  • 19
    • 0029215231 scopus 로고
    • Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm
    • Wurth, B., Eckl, K., Antreich, K,: Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm. 32th Design Automation Conference, (1995) 54-59
    • (1995) 32th Design Automation Conference , pp. 54-59
    • Wurth, B.1    Eckl, K.2    Antreich, K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.