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Technology Mapping for TLU FPGAs Based on Decomposition of Binary Decision Diagrams
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Chang, S.C.1
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0028259317
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FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Design
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Cong, J., Ding, Y.: FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13(1) (1994) 1-12
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An Optimal Performance-driven Technology Mapping Algorithm for LUT based FPGAs under arbitrary net-delay models
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On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping
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Cong, J., Ding, Y.: On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. 30th Design Automation Conference (DAC), (1993) 213-218
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Cong, J.1
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0029707981
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Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design
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Cong, J., Hwang, Y. Y.: Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. 33th Design Automation Conference, (1996) 726-729
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Cong, J.1
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Technology Mapping of Lookup Table Based FPGAs for Performance
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An Iterative Area/Performance Trade-Off Algorithm for LUT-Based FPGA Technology Mapping
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Huang, J. D., Jou, J. Y., Shen, W. Z.: An Iterative Area/Performance Trade-Off Algorithm for LUT-Based FPGA Technology Mapping. IEEE International Conference on Computer-Aided Design, (1996) 13-17
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33th Design Automation Conference
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Legl, C., Wurth, B., Eckl, K.: A Boolean Approach to Performance-Directed Technology Mapping for LUT-based FPGA Designs. 33th Design Automation Conference, (1996) 730-733
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A Boolean Approach to Performance-Directed Technology Mapping for Lut-Based FPGA Designs
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DART: Delay and Routability Driven Technology Mapping for LUT Based FPGAs
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Lu, A., Dagless, E., Saul, J.: DART: Delay and Routability Driven Technology Mapping for LUT Based FPGAs. International Conference on Computer Design (ICCD), (1995) 409-414
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Tradeoff literals against support for Logic Synthesis of LUT based FPGAs
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Lu, A., Dagless, E., Saul, J.: Tradeoff literals against support for Logic Synthesis of LUT based FPGAs. IEE Proceedings on Computers and Digital Techniques, 143(2) (1996) 111-119
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Sangiovanni-Vincentelli, A.: Performance Directed Synthesis for Table Look Up Programmable Gate Arrays
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Routability-Driven Technology Mapping for Lookup Table-Based FPGAs
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Schlag, M., Kong, J., Chan, P. K.: Routability-Driven Technology Mapping for Lookup Table-Based FPGAs. International Conference on Computer Design: VLSI in Computer and Processors, (1992) 86-90
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Memorandum No. UCB/ERL M/92/41, Electronics Research Laboratory, University of California, Berkeley
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Sentovich, E., Singh, K. J., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P. R., Brayton, R. K., Sangiovanni-Vincentelli, A.: SIS: A System for Sequential Circuit Synthesis. Memorandum No. UCB/ERL M/92/41, Electronics Research Laboratory, University of California, Berkeley, (1992)
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SIS: A System for Sequential Circuit Synthesis
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0028697847
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Maple: A simultaneous technology mapping, placement, and global routing algorithm for Field-Programmable Gate Arrays
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Togawa, N., Sato, M., Ohtsuki, T.: Maple: A simultaneous technology mapping, placement, and global routing algorithm for Field-Programmable Gate Arrays. IEEE International Conference on Computer-Aided Design, (1994) 156-163
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0029215231
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Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm
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Wurth, B., Eckl, K., Antreich, K,: Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm. 32th Design Automation Conference, (1995) 54-59
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32th Design Automation Conference
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Wurth, B.1
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Antreich, K.3
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