Effect of CMOS technology scaling on thermal management during burn-in

IEEE Transactions on Semiconductor Manufacturing

Volumn 16, Issue 4, 2003, Pages 686-695

  Semenov, Oleg ^a   Vassighi, Arman ^a   Sachdev, Manoj ^a   Keshavarzi, Ali ^b   Hawkins, C F ^c  

^a UNIVERSITY OF WATERLOO   (Canada)

^b INTEL CORPORATION   (United States)

^c University of New Mexico   (United States)

Author keywords

Burn in testing; CMOS technology scaling; Junction temperature; Thermal management

Indexed keywords

CMOS INTEGRATED CIRCUITS; HIGH TEMPERATURE OPERATIONS; INTEGRATED CIRCUIT TESTING; LEAKAGE CURRENTS; SEMICONDUCTOR JUNCTIONS; THERMODYNAMIC STABILITY;

BURN-IN TESTING; CMOS TECHNOLOGY SCALING; JUNCTION TEMPERATURE; THERMAL MANAGEMENT;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0344896817     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2003.818985     Document Type: Article

References (37)

1. S. Borkar, "Design challenges of technology scaling," IEEE Micro, pp. 23-29, July-Aug. 1999.
2. S. Rusu. Trends and challenges in VLSI technology scaling toward 100 nm. presented at ESSCIRC. [Online]. Available:http://www.esscirc.org/esscirc2001/C01_Presentations/404.pdf.
3. S. Thompson, P. Packan, and M. Bohr. (1998) MOS scaling: Transistor challenges for the 21st century. Intel Technol. J. [Online], pp. 1-19 Available:http://developer.intel.com/technology/itj/archive.htm.
4. J. Ahn, H. -S. Kim, T. -J. Kim, H. H. Shin, Y. H. Kim, D. -U. Lim, J. Kim, U. Chung, S. -C. Lee, and K. -P. Suh, "1 GHz microprocessor integration with high performance transistor and low RC delay," in IEDM Tech. Dig., 1999, pp. 28.5.1-28.5.4
5. T. J. Goh, A. N. Amir, C. -P. Chiu, and J. Torresola, "Novel thermal validation metrology based on nonuniform power distribution for Pentium III Xeon cartridge processor design with integrated level two cache," in Proc. Electronic Components and Technology Conf., 2001, pp. 1181-1186.
6. S. H. Gunter, F. Binns, D. M. Carmean, and J. C. Hall. (2001) Managing the impact of increasing microprocessor power consumption. Intel Technol. J. [Online], pp. 1-9 Available: http://developer.intel.com/technology/itj/archieve.htm.
7. Y. K. Cheng, C. -C. Teng, A. Dharchoudhury, E. Rosenbaum, and S. -M. Kang, "A chip-level electrothermal simulator for temperature profile estimation of CMOS VLSI chips," in Proc. Int. Symp. Circuit Systems, 1996, pp. 580-583.
8. C. -C. Teng, Y. K. Cheng, E. Rosenbaum, and S. M. Kang, "iTEM: A temperature-dependent electromigration reliability diagnosis tool," IEEE Trans. Computer-Aided Design, vol. 16, pp. 882-893, Aug. 1997.
9. P. Reed, M. Alexander, J. Alvarez, M. Brauer, C. -C. Chao, C. Croxton, L. Eisen, T. Le, T. Ngo, C. Nicoletta, H. Sanchez, S. Taylor, N. Vanderschaaf, and G. Gerosa, "A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cash controller," IEEE J. Solid-State Circuits, pp. 1635-1649, Nov. 1997.
10. 2 dielectrics," Appl. Phys. Lett., vol. 71, no. 8, pp. 1101-1103, 1997.
11. A. M. Yassine, H. E. Nariman, M. McBride, M. Uzer, and K. R. Olasupo, "Time dependent breakdown of ultra-thin gate oxide," IEEE Trans. Electron Devices, vol. 47, pp.1416-1420, July 2000.
12. J. H. Suehle, "Ultra thin gate oxide reliability: Physical models, statistics, and characterization," IEEE Trans. Electron Devices, vol. 49, pp. 958-971, June 2002.
13. P.E. Nicollian, W. R. Hunter, and J. C. Hu, "Experimental evidence for voltage driven breakdown models in ultra thin gate oxides," Proc. IEEE Int. Reliability Physics Symp., pp. 7-15, 2000.
14. ox < 32Å)," Proc. IEEE Int. Reliability Workshop (IRW), pp. 20-25, 2001.
15. P. Lall, "Tutorial: Temperature as an input to microelectronics-reliability models," IEEE Trans. Reliability, vol. 45, pp. 3-9, Jan. 1996.
16. J. B. Bowles, "A survey of reliability-prediction procedures for microelectronics devices," IEEE Trans. Reliability, vol. 41, pp. 2-12, Jan. 1992.
17. R. Viswanath, V. Wakharkar, A. Watwe, and V. Lebonheur. (2000) Thermal performance challenges from silicon to systems. Intel Technol. J. pp. 1-16 Available: http://developer.intel.com/technology/itj/archive.htm.
18. P. Tadayon. (2000) Thermal challenges during microprocessor testing. Intel Technol. J. [Online], pp. 1-8 Available: http://developer.intel.com/technology/itj/archive.htm
19. R. C. Joy and E. S. Schlig, "Thermal properties of very fast transistors," IEEE Trans. Electron Devices, vol. ED-17, pp. 586-594, Aug. 1970.
20. N. Rinaldi, "Thermal analysis of solid-state devices and circuits: An analytical approach," Solid-State Electron., vol. 44, pp. 1789-1798, 2000.
21. N. Rinaldi, "On the modeling of the transient thermal behavior of semiconductor devices," IEEE Trans. Electron Devices, vol. 48, pp. 2796-2802, Dec. 2001.
22. D. L. Blackburn and A. R. Hefner, "Thermal components models for electro-thermal network simulation," Proc. 9th IEEE Semi-Therm Symp., pp. 88-98, 1993.
23. B. Davari, R. H. Dennard, and G. G. Shahidi, "CMOS scaling for high performance and low power - The next ten years," Proc. IEEE, vol. 83, pp. 595-606, Apr. 1995.
24. M. Borah, R. M. Owens, and M. J. Irwin "Transistor sizing for low power CMOS circuits," IEEE Trans. Computer-Aided Design, vol. 15, pp. 665-671, June 1996.
25. D. P. Valett and J. M. Soden "Finding fault with deep-submicron ICs," IEEE Spectrum, pp. 39-50, Oct. 1997.
26. International Technology Roadmap for Semiconductors [Online]. Available: http://public.itrs.net
27. L. W. Ivy, Jr., P. Godavarti, N. Alizy, T. Mckenzie, and D. Mitchell "Sacrificial metal wafer level burn-in KGD," Proc. IEEE Electronic Components Technology Conf., pp. 535-540, 2000.
28. J. Novitsky and D. Pedersen "Form factor introduces an integrated process for wafer-level packaging, burn-in test, and module level assembly," Proc. IEEE Int. Symp. Advanced Packaging Materials, pp. 226-231, 1999.
29. G. Kromann "Thermal management of a C4/CBGA interconnect technology for a high-performance RISC microprocessor: The Motorola PowerPC 620™ microprocessor," Proc. IEEE Electronic Technology Conf., pp. 652-659, 1996.
30. A. W. Righter, C. F. Hawkins, J. M. Soden, and P. Maxwell "CMOS IC reliability indicators and burn-in economics," in Proc. Int. Test Conf., 1998, pp. 194-203.
31. N. F. Dean and A. Gupta "Characterization of a thermal interface material for burn-in application," Proc. IEEE Thermal Thermomechanical Phenomena Electronic Syst., pp. 36-41, 2000.
32. W. Wondrak "Physical limits and lifetime limitations of semiconductor devices at high temperature," Microelectronics Reliability, vol. 39, no. 6-7, pp. 1113-1120, 1999.
33. H. Sanchez, B. Kuttanna, T. Olson, M. Alexander, G. Gerosa, R. Philip, and J. Alvarez "Thermal management system for high performance PowerPC microprocessors," Proc. IEEE COMPCON, pp. 325-330, 1997.
34. [Online]. Available: http://www.despatch.com/pdfs/PBC.pdf
35. T. Kim, W. Kuo, and W.-T. K. Chien "Burn-in effect on yield," IEEE Trans. Electron. Packaging Manuf., vol. 23, no. 4, pp. 293-299, 2000.
36. A. Vassighi, O. Semenov, and M. Sachdev "Impact of power dissipation on burn-in test environment for sub-micron technologies," Proc. IEEE Int. Workshop Yield Optimization and Test, 2001.
37. T. M. Mak "Is CMOS more reliable with scaling?," presented at the IEEE Int. On-Line Testing Workshop, July 2002.