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Volumn 2, Issue 2, 1997, Pages 151-167

Board-level multiterminal net routing for FPGA-based logic emulation

Author keywords

Board level routing; Crossbars; Field programmable gate arrays; Logic emulation; Multi terminal net decomposition

Indexed keywords


EID: 0344667944     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/253052.253136     Document Type: Article
Times cited : (11)

References (13)
  • 8
    • 0042096221 scopus 로고
    • Multiplexing enhances hardware emulation
    • MALINIAK, L. 1992. Multiplexing enhances hardware emulation. Electronic Des. (Nov.), 76-78.
    • (1992) Electronic Des. , Issue.NOV , pp. 76-78
    • Maliniak, L.1
  • 9
    • 0004001583 scopus 로고
    • TRIMBERGER, S. (ED.) Kluwer, Amsterdam, The Netherlands
    • TRIMBERGER, S. (ED.) 1994. Field-Programmable Gate Array Technology, Kluwer, Amsterdam, The Netherlands.
    • (1994) Field-programmable Gate Array Technology
  • 10
    • 0027614653 scopus 로고
    • An efficient logic emulation system
    • VARGHESE, J., BUTTS, M., AND BATCHELLER, J. 1993. An efficient logic emulation system. IEEE Trans. VLSI 1, (June), 171-174.
    • (1993) IEEE Trans. VLSI , vol.1 , Issue.JUNE , pp. 171-174
    • Varghese, J.1    Butts, M.2    Batcheller, J.3
  • 11
    • 0026173694 scopus 로고
    • Computer-aided prototyping for ASIC-based systems
    • WALTERS, S. 1991. Computer-aided prototyping for ASIC-based systems. IEEE Des. Test (June), 4-10.
    • (1991) IEEE Des. Test , Issue.JUNE , pp. 4-10
    • Walters, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.