Synchronization design of a coupled phase-locked loop

IEEE Transactions on Microwave Theory and Techniques

Volumn 51, Issue 3, 2003, Pages 952-960

  Buckwalter, James F ^a   Heath, Ted H ^b   York, Robert A ^a  

^a University of California   (United States)

^b GEORGIA TECH RESEARCH INSTITUTE   (United States)

Author keywords

Coupled phase locked loop (CPLL); Hold in range; Pull in range; Time delay

Indexed keywords

ANTENNA PHASED ARRAYS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; LOW PASS FILTERS; MIXER CIRCUITS; POLES AND ZEROS; SYNCHRONIZATION; VARIABLE FREQUENCY OSCILLATORS;

COUPLED PHASE-LOCKED LOOP; HOLD-IN RANGE; PULL-IN RANGE; TIME DELAY;

PHASE LOCKED LOOPS;

EID: 0344520305     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2003.808701     Document Type: Article

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