Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics

Proceedings - 16th Conference on Advanced Research in VLSI, ARVLSI 1995

Volumn , Issue , 1995, Pages 200-211

  Cai, X ^a   Nabors, K ^a   White, J ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY ELEMENT METHOD; CAPACITANCE; DIELECTRIC MATERIALS; EXTRACTION; SAILING VESSELS; VLSI CIRCUITS;

ACCELERATED PROGRAMS; CAPACITANCE EXTRACTION; COLLOCATION METHOD; DIELECTRIC INTERFACE; DIELECTRIC MEDIUM; EFFICIENT IMPLEMENTATION; GALERKIN TECHNIQUE; PIECE-WISE CONSTANTS;

GALERKIN METHODS;

EID: 0343559296     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.1995.515621     Document Type: Conference Paper

References (16)

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