Spin-etch planarization for dual damascene interconnect structures

Solid State Technology

Volumn 43, Issue 3, 2000, Pages

  DeBear, Donald S ^a   Levert, Joseph A ^b   Mukherjee, Shyama P ^b  

^a SEZ America Inc   (United States)

^b Honeywell Electronic Materials   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; DIELECTRIC MATERIALS; ELECTROPLATING; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS; SUBSTRATES;

CHEMICAL MECHANICAL PLANARIZATION; PROCESS METROLOGY; SPIN ETCH PLANARIZATION;

ETCHING;

EID: 0343517477     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (4)

1. D.C. Edelstein, "Advantages of Copper Interconnects," Proceedings of the 12th International IEEE VLSI Multilevel Interconnection Conference, p. 301, 1995.
2. D.T. Price, R.J. Gutman, S.P. Murarka, Thin Solid Films, 308-309, pp. 523-528, 1997.
3. J. Levert, S. Mukherjee, D. DeBear, "A Novel Spin-Etch Planarization Approach for Dual Damascene Copper Interconnects," ECS Conference, Hawaii, October 1999.
4. J. Levert, S. Mukherjee, D. DeBear, "Spin-Etch Planarization Process for Copper Damascene Interconnects," SEMICON Japan, December 1999.