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Volumn 45, Issue 1, 1996, Pages 13-19

A new residue arithmetic error correction scheme

Author keywords

Error correction; Error detection; Fault tolerant computing; Parallel algorithms; Redundant residue number system; Residue number system

Indexed keywords


EID: 0343152325     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.481482     Document Type: Article
Times cited : (25)

References (15)
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    • Barsi, F.1    Maestrini, P.2
  • 6
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    • Ramachandran, V.1
  • 7
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  • 8
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    • Etzel, M.H.1    Jenkins, W.K.2
  • 10
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    • Multiple burst correction with the Chinese Remainder theorem
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    • J.J. Stone, "Multiple burst correction with the Chinese Remainder theorem," J. SIAM, vol. 11, no. 1, pp. 74-81, Mar. 1963.
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  • 11
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    • Apr.
    • E.D. Di Claudio, G. Orlandi, and F. Piazza, "A systolic redundant residue arithmetic error correction circuit," IEEE Trans. Computers, vol. 42, no. 4, pp. 427-432, Apr. 1993.
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  • 13
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    • Piestrak, S.J.1
  • 14
    • 0024048838 scopus 로고
    • Fault tolerance in a systolic residue arithmetic processor array
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    • R.J. Cosentino, "Fault tolerance in a systolic residue arithmetic processor array," IEEE Trans. Computers, vol. 37, no. 7, pp. 886-890, July 1988.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.