Design and implementation of a real-time hierarchical parallel postprocessor for 100 keV electron beam lithography

Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures

Volumn 15, Issue 6, 1997, Pages 2204-2208

  Muray, Lawrence P ^a   Anderson, Erik H ^a   Boegli, Volker ^a  

^a LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0342952428     PISSN: 10711023     EISSN: None     Source Type: Journal    
DOI: 10.1116/1.589614     Document Type: Article

References (5)

1. SIA Roadmap, 1994.
2. M. Hintermaier, U. Hofmann, B. Hübner, C. K. Kalus, E. Knapek, H. W. P. Koops, R. Schlager, E. Seebald, and M. Weber, J. Vac. Sci. Technol. B 9, 3043 (1991).
3. S. Wind, T. J. Watson Research Center, IBM (private communication).
4. T. R. Groves, J. Vac. Sci. Technol. B 11, 2746 (1993).
5. E. H. Anderson, L. P. Muray, and V. Boegli, J. Vac. Sci. Technol. B (submitted).