A PLL clock generator with 5 to 110MHz lock range for microprocessors

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 1992-February, Issue , 1992, Pages 50-51

  Young, Ian A ^a   Greason, Jeff K ^a   Smith, Jeff E ^a   Wong, Keng L ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CLOCKS; LOCKS (FASTENERS);

BLOCK DIAGRAMS; CLOCK GENERATOR; CMOS TECHNOLOGY; FULLY INTEGRATED; PEAK-TO-PEAK JITTER; PHASE LOCKED LOOP (PLL); SUPPLY VOLTAGES;

PHASE LOCKED LOOPS;

EID: 0342886911     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.1992.200405     Document Type: Conference Paper

References (4)

1. Schutz, J., "A 100MHz Microprocessor", ISSCC 1991 DIGEST OF TECHNICAL PAPERS, pp. 90-91, Feb. 1991.
2. Kim, B., and P. Gray, "A 30MHz Hybrid Analog/Digital Clock Recovery Circuit in 2pm CMOS", IEEE J. Solid-State Circuits, pp. 1385-1394, Dec. 1990.
3. Johnson, M., and E. Hudson, "A Variable Delay Line PLL For CPU-Coprocessor Synchronization", IEEE J. Solid-State Circuits, pp. 1218-1223, Oct. 1988.
4. Moon, G., et al., "An Enhancement-Mode Voltage-Controlled Linear Resistor with Large Dynamic Range", IEEE Trans. Circuits & Systems, p. 1284, Oct. 1990.