Modeling of jitter in bang-bang clock and data recovery circuits

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 711-714

  Lee, Jri ^a   Kundert, Kenneth S ^b   Razavi, Behzad ^a  

^a University of California   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; INTEGRATED CIRCUIT LAYOUT; JITTER; MATHEMATICAL MODELS;

BANG-BANG PHASE DETECTORS; CLOCK AND DATA RECOVERY CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0242695824     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. J. D. H. Alexander, "Clock Recovery from Random Binary Data," Electronics Letters, vol. 11, pp.541-542, Oct. 1975.