Single-chip FEC codec using a concatenated BCH code for 10 Gb/s long-haul optical transmission systems

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 279-282

  Seki, K ^a   Mikami, K ^b   Katayama, A ^a   Suzuki, S ^a   Shinohara, N ^b   Nakabayashi, M ^b  

^a NEC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CODES (SYMBOLS); DECODING; ERROR CORRECTION; ITERATIVE METHODS; OPTICAL SYSTEMS;

FORWARD ERROR CORRECTION; ITERATIVE DECODING; OPTICAL TRANSMISSION SYSTEMS;

CMOS INTEGRATED CIRCUITS;

EID: 0242611975     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. ITU-T G.975, "Forward error correction for submarine systems"
2. ITU-T G.709, "Network node interface for the optical transport network"
3. J. Yoshimura, K.Suzuki, T.Ohsumi, "10Gb/s × 105 DWDM SLTE with Super-FEC transponder," SubOptic, 2001, T4.4.4.
4. T. Mizouch et al., "Transparent multiplexer featuring Super-FEC for optical transport networking," SubOptic, 2001, P4.2.3.
5. ITU-T G.798, "Characteristics of optical transport networks (OTN) hierarchy equipment functional blocks"
6. K. Seki et al., "Single-chip 10.7 Gb/s FEC codec LSI using time-multiplexed RS decoder", CICC, 2001, 13-2.
7. H.Okano and H.Imai, "A construction method of high-speed decoders using ROM's for Bose-Chaudhuri-Hocquenghem and Reed-Solomon codes", IEEE Trans. On Computers, vol. C-36, NO. 10, October 1987.