Near speed-of-light on-chip electrical interconnect

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 18-21

  Chang, Richard T ^a   Yue, C Patrick ^a   Wong, S Simon ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC FREQUENCY MEASUREMENT; INDUCTANCE MEASUREMENT; MICROPROCESSOR CHIPS; SILICA;

ELECTRICAL SIGNAL PROPAGATION; ON CHIP ELECTRICAL INTERCONNECT;

INTERCONNECTION NETWORKS;

EID: 0242611679     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. M. Bohr. "Interconnect Scaling - The Real Limiter to High Performance ULSI," International Electron Devices Meeting Digest, 1995, 241-244.
2. D. Miller. "Rationale and Challenges for Optical Interconnects to Electronic Chips," Proceedings of the IEEE, vol. 88, Issue 6, June 2000, p. 728-749.
3. H. B. Bakoglu. Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, 1990.
4. M. Bazes. "Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers," IEEE Journal of Solid-State Circuits, vol. 26, No. 2, Feb. 1991, p. 165-168.