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Volumn 14, Issue 8, 2003, Pages 1357-1363

Study on the low power technology of software pipeline

Author keywords

Compiler optimization; Dynamic frequency scalable; Low power; Parallel processing; Software pipeline

Indexed keywords

CALCULATIONS; COMPUTER SOFTWARE; FORMAL LOGIC; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; SCHEDULING;

EID: 0242607595     PISSN: 10009825     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (4)

References (8)
  • 4
    • 0002017307 scopus 로고
    • Instruction-level parallel processing: History, overview and perspective
    • Rau BR, Fisher JA. Instruction-level parallel processing: History, overview and perspective. Journal of Supercomputing, 1993, 7(1/2): 9-50.
    • (1993) Journal of Supercomputing , vol.7 , Issue.1-2 , pp. 9-50
    • Rau, B.R.1    Fisher, J.A.2
  • 5
    • 0036621225 scopus 로고    scopus 로고
    • A multithreaded compiler optimization technology with low power
    • Chinese source
    • Zhao RC, Tang ZM, Zhang ZQ, Gao GR. A multithreaded compiler optimization technology with low power. Journal of Software, 2002, 13(6): 1123-1129 (in Chinese with English abstract).
    • (2002) Journal of Software , vol.13 , Issue.6 , pp. 1123-1129
    • Zhao, R.C.1    Tang, Z.M.2    Zhang, Z.Q.3    Gao, G.R.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.