Transformation of VHDL descriptions into DEVS models for fault modeling

Proceedings of the IEEE International Conference on Systems, Man and Cybernetics

Volumn 2, Issue , 2003, Pages 1205-1210

  Capocchi, Laurent ^a   Bernardi, Fabrice ^a   Federici, Dominique ^a   Bisgambiglia, Paul ^a  

^a UNIVERSITÉ DE CORSE   (France)

Author keywords

DEVS formalism; Fault; Modeling; Simulation; VHDL descriptions

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; DISCRETE TIME CONTROL SYSTEMS; FAILURE ANALYSIS; SET THEORY; SIMULATORS;

DISCRETE EVENT SYSTEMS; FAULT; SOFTWARE PACKAGE PYTHON-DEVS;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 0242576361     PISSN: 08843627     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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