A Flexible Architecture for Digital Signal Processing

IEICE Transactions on Information and Systems

Volumn E86-D, Issue 10, 2003, Pages 2179-2186

  Boonkumklao, Wichai ^a   Miyanaga, Yoshikazu ^a   Dejhan, Kobchai ^b  

^a HOKKAIDO UNIVERSITY   (Japan)

^b NONE

Author keywords

FRM; IP; PCA; Reconfigurable architecture; VHDL

Indexed keywords

DIGITAL FILTERS; FIELD PROGRAMMABLE GATE ARRAYS; INTELLECTUAL PROPERTY; LSI CIRCUITS; MASKS;

FREQUENCY RESPONSE MASKING (FRM);

DIGITAL SIGNAL PROCESSING;

EID: 0242494295     PISSN: 09168532     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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