A 62.5Gb/s multi-standard SerDes IC

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 585-588

  Partovi, Hamid ^a   Evans, Bill ^b   Wilson, Tom ^b   Shelton, Scott ^b   Naviasky, Eric ^b   Sanjeevi, Ethiraj ^a   Wen, Yongli ^a   Gopalakrishnan, Karthik ^a   Chokkalingam, Sivaraman ^a   Thompson, Hugh ^b   Casas, Mike ^b   Ye, Lingting ^b   Hufford, Mike ^b   Qiu, Yujing ^a   Williams, Michelle ^b   James, Jared ^b   Baldisserotto, Alberto ^b   White, Steven ^b   Williams, Steve ^b   Georgantas, Domenic ^b   Gray, Tom ^b   more..

^a INFINEON TECHNOLOGIES   (United States)

^b Cadence Design Services   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; JITTER; NETWORK PROTOCOLS; PHASE LOCKED LOOPS; TIMING CIRCUITS; VARACTORS;

CLOCK SYNTHESIS; PHASE NOISE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0242443637     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Optical Internetworking Forum, OIF-SF15-01.0 Implementation Agreement, Jan. 2001.
2. Margarit, M., et al., "A Low-Noise Low-Power VCO with Automatic Amplitude Control for Wireless Applications," Journal of Solid State Circuits, June 1999.
3. Optical Internetworking Forum, OIF2001.149, "SxI-5: Electrical Characteristics of Common I/Os for SFI-5 and SPI-5," Oct. 2002.
4. Alexander, J. D. H., "Clock Recovery from Random Binary Signals," Electronic Letters, Oct. 1975.
5. Optical Internetworking Forum, OIF-SFI4-01.0 Implementation Agreement, Sep. 2000.