Low power gate resizing of combinational circuits by buffer-redistribution

Proceedings - 20th Anniversary Conference on Advanced Research in VLSI, ARVLSI 1999

Volumn , Issue , 1999, Pages 170-184

  Sundararajan, Vijay ^a   Parhi, Keshab K ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT TESTING; ITERATIVE METHODS; POLYNOMIAL APPROXIMATION; TIMING CIRCUITS; VLSI CIRCUITS;

BENCHMARK CIRCUIT; CRITICAL PATHS; EXACT ALGORITHMS; MAPPING TECHNIQUES; POLYNOMIAL-TIME; POWER REDUCTIONS; SUBOPTIMAL SOLUTION; TRANSFORMATION TECHNIQUES;

LOW POWER ELECTRONICS;

EID: 0142239539     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.1999.756047     Document Type: Conference Paper

References (19)

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