Fault Injection for Verifying Testability at the VHDL Level

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 131-137

  Seward, S R ^a   Lala, P K ^a  

^a 3202 Bell Engineering Center   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL CIRCUITS; HIGH LEVEL LANGUAGES; TESTING;

INJECTION TECHNIQUE;

ELECTRIC FAULT CURRENTS;

EID: 0142216021     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. T. Delong et al., "A Fault Injection Technique for VHDL Behavioral-Level Models", IEEE Design & Test of Computers, 1996, pp. 24-33
2. B .Parrotta et al., "New Techniques for Accelerating Fault Injection in VHDL Descriptions", IEEE 2000 Online Testing Workshop, pp. 61-66
3. F. Vargas et al., "Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL", IEEE 2000 Online Testing Workshop, pp. 67.
4. N.Z.Basturkmen et al., "A Low Power Pseudo-Random BIST Technique", IEEE 2002 Online Testing Workshop, pp. 140
5. A.Manzone et al., "Fault Insertion and Verification: A Case Study", IEEE 2002 Online Testing Workshop, p. 44.
6. R.J. Hayne and B.W. Johnson, "Behavioral Fault Modeling in a VHDL Synthesis Environment," Proceedings VLSI Test Symposium, April 1999, pp. 333-340.
7. D.Mavis et al., "SEU and SET Mitigation Techniques for FPGA Circuit and Configuration Bit Storage Design", 2000 MAPLD International Conference
8. P. Civera et al., "Exploiting FPGA for accelerating Fault Injection experiments", IEEE 2001 Online Testing Workshop, pp. 9.
9. Parag K.Lala, Self-Checking and Fault Tolerant Digital Design, Morgan Kaufmann Publishers, 2001.