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Volumn 1, Issue , 2002, Pages 549-553

Implementation of the DTMROC-S ASIC for the ATLAS TRT Detector in a 0.25μm CMOS technology

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; IONIZATION; MICROPROCESSOR CHIPS; RADIATION HARDENING; SIGNAL PROCESSING;

EID: 0142210229     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (8)

References (9)
  • 2
    • 0142143770 scopus 로고    scopus 로고
    • Total dose and Single Event Effects (SEE) in a 0.25μm CMOS technology
    • INFN Rome, September
    • F. Faccio et al., "Total dose and Single Event Effects (SEE) in a 0.25μm CMOS technology", LEB98, INFN Rome, September 1998, pp.105-113.
    • (1998) LEB98 , pp. 105-113
    • Faccio, F.1
  • 3
    • 17944374804 scopus 로고    scopus 로고
    • Progress in the development of the DTMROC time measurement chip
    • C. Alexander et al., "Progress in the development of the DTMROC time measurement chip", IEEE Trans. Nucl. Sci., vol.48 (2001), pp.514-519.
    • (2001) IEEE Trans. Nucl. Sci. , vol.48 , pp. 514-519
    • Alexander, C.1
  • 4
    • 0035428748 scopus 로고    scopus 로고
    • Implementation of the ASDBLR straw tube readout ASIC in DMILL technology
    • N. Dressandt et al., "Implementation of the ASDBLR straw tube readout ASIC in DMILL technology", IEEE Trans. Nucl. Sci., vol.48 (2001), pp. 1239-1243.
    • (2001) IEEE Trans. Nucl. Sci. , vol.48 , pp. 1239-1243
    • Dressandt, N.1
  • 6
    • 0142236659 scopus 로고    scopus 로고
    • A Configurable Radiation Tolerant Dual-Ported Static RAM macro, designed in a 0.25μm CMOS technology for applications in the LHC environment
    • Colmar, France, September
    • K. Kloukinas et al., "A Configurable Radiation Tolerant Dual-Ported Static RAM macro, designed in a 0.25μm CMOS technology for applications in the LHC environment", LEB02, Colmar, France, September 2002.
    • (2002) LEB02
    • Kloukinas, K.1
  • 7
    • 0142205744 scopus 로고    scopus 로고
    • Synopsys Inc., 700 East Middlefield Rd., Mountain View, CA 94043
    • Synopsys Inc., 700 East Middlefield Rd., Mountain View, CA 94043.
  • 8
    • 0142205743 scopus 로고    scopus 로고
    • Cadence Design System Inc., 555 N. Mitilda Ave., Sunnyville, CA 94086
    • Cadence Design System Inc., 555 N. Mitilda Ave., Sunnyville, CA 94086.
  • 9
    • 0002068378 scopus 로고    scopus 로고
    • SEU effects in registers and in a Dual-Ported Static RAM designed in a 0.25μm CMOS technology for applications in the LHC
    • Snowmass, USA, September
    • F. Faccio et al., "SEU effects in registers and in a Dual-Ported Static RAM designed in a 0.25μm CMOS technology for applications in the LHC", LEB99, Snowmass, USA, September 1999, pp.571-575.
    • (1999) LEB99 , pp. 571-575
    • Faccio, F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.