3.21 ps ECL gate using InP/InGaAs DHBT technology

Electronics Letters

Volumn 39, Issue 20, 2003, Pages 1434-1436

  Ishii, K ^a   Nosaka, H ^a   Ida, M ^a   Kurishima, K ^a   Shibata, T ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; HETEROJUNCTION BIPOLAR TRANSISTORS; LOGIC GATES; METALLORGANIC VAPOR PHASE EPITAXY;

OSCILLATION FREQUENCY;

SEMICONDUCTING INDIUM GALLIUM ARSENIDE;

EID: 0142020830     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20030940     Document Type: Article

References (4)

1. SRIVASTAVA, M.K., RAGHAVAN, R., THIAGARAJAH, R., CASE, M.G., ARNOLD, E., POBANZ, C.W., NIELSEN, S.O., YEN, J.C., and JOHNSON, R.A.: 'InP HBT ring oscillator with 2.0 ps/stage gate delay'. GaAs IC Symp. Tech. Dig., 2002, pp. 171-174
2. max SiGe technology', IEEE Electron Device Lett., 2002, 23, pp. 541-543
3. ISHII, K., ICHINO, H., TOGASHI, M., KOBAYASHI, Y., and YAMAGUCHI, C.: 'Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops', IEEE J. Solid-State Circuits, 1995, 30, pp. 19-24
4. KURISHIMA, K., IDA, M., and WATANABE, N.: 'InP double-heterojunction bipolar transistors with a carbon-doped graded'. Extended Abstracts of the 2002 Int. Conf. on Solid State Devices and Materials, 2002, Florence, Italy, pp. 272-273