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Volumn , Issue , 1998, Pages 835-839

A dynamic model for the state assignment problem

Author keywords

[No Author keywords available]

Indexed keywords

ASSIGNMENT ALGORITHMS; ASSIGNMENT PROBLEMS; CONSTRAINT GENERATION; DYNAMIC CONSTRAINTS; ENCODING PROCESS; INPUT MODELING; INPUT OUTPUT MODEL; STANDARD TOOLS;

EID: 0141977502     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655955     Document Type: Conference Paper
Times cited : (5)

References (10)
  • 3
    • 84939338348 scopus 로고
    • Multiplevalued minimization for pla optimization
    • September
    • R. Rudell and A. L. Sangiovanni-Vincentelli: "Multiplevalued Minimization for PLA Optimization", IEEE Trans. on CAD, Vol. CAD-6, pp.727-751, September 1987.
    • (1987) IEEE Trans. on CAD , vol.CAD-6 , pp. 727-751
    • Rudell, R.1    Sangiovanni-Vincentelli, A.L.2
  • 4
    • 0026900072 scopus 로고
    • Symbolic minimization of multilevel logic and the input encoding problem
    • July
    • S. Malik, L. Lavagno, R.K. Brayton and A. Sangiovanni-Vincentelli, "Symbolic Minimization of Multilevel Logic and the Input Encoding Problem", IEEE Trans. on CAD, Vol. 11, no. 7, pp. 825-843, July 1992.
    • (1992) IEEE Trans. on CAD , vol.11 , Issue.7 , pp. 825-843
    • Malik, S.1    Lavagno, L.2    Brayton, R.K.3    Sangiovanni-Vincentelli, A.4
  • 5
    • 0024701606 scopus 로고
    • Efficiency of state assignment methods for pla-based sequential circuits
    • July
    • J.L. Huertas y J.M. Quintana: "Efficiency of State Assignment Methods for PLA-Based Sequential Circuits", IEE Proc., Vol. 136, Pt E, no. 4, pp. 247-250, July 1989.
    • (1989) IEE Proc. , vol.136 , Issue.4 , pp. 247-250
    • Huertas, J.L.1    Quintana, J.M.2
  • 6
    • 0025489532 scopus 로고
    • Nova: State assignment of finite state machines for optimal two-level logic implementation
    • Sept.
    • T. Villa y A.L. Sangiovanni-Vincentelli: "NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementation", IEEE Trans. on CAD, Vol. CAD-9, no. 9, pp. 905-923, Sept. 1990.
    • (1990) IEEE Trans. on CAD , vol.CAD-9 , Issue.9 , pp. 905-923
    • Villa, T.1    Sangiovanni-Vincentelli, A.L.2
  • 7
    • 0027885630 scopus 로고
    • An efficient algorithm for constrained encoding and its applications
    • Dec.
    • C.J. Shi and J.A. Brzozowski, "An efficient Algorithm for Constrained Encoding and Its applications", IEEE Trans. on CAD, V.12, no.12, pp. 1813-1826, Dec. 1993.
    • (1993) IEEE Trans. on CAD , vol.12 , Issue.12 , pp. 1813-1826
    • Shi, C.J.1    Brzozowski, J.A.2
  • 8
    • 0022791754 scopus 로고
    • Symbolic design of combinational and sequential logic circuits implemented by two-level macros
    • September
    • G. de Micheli, "Symbolic design of Combinational and Sequential Logic Circuits Implemented by Two-Level Macros", IEEE Trans. on CAD, Vol. 5, pp. 597-616, September 1986.
    • (1986) IEEE Trans. on CAD , vol.5 , pp. 597-616
    • De Micheli, G.1
  • 9
    • 0025844173 scopus 로고
    • Exact algorithms for output encoding, state assignment and four levelboolean minimization
    • January
    • S. Devadas and A. R. Newton, "Exact Algorithms for Output encoding, State Assignment and Four LevelBoolean Minimization", IEEE Trans. on CAD, Vol. 10, no. 1, pp. 13-27, January 1991.
    • (1991) IEEE Trans. on CAD , vol.10 , Issue.1 , pp. 13-27
    • Devadas, S.1    Newton, A.R.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.