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Volumn 31, Issue 5, 2003, Pages 453-464

Analytical transient response of MOS current mirrors

Author keywords

Circuit simulation; Current mirror; Macromodelling; Settling time; Transient response

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENTS; FUNCTIONS; MATHEMATICAL MODELS; PARAMETER ESTIMATION; TRANSIENTS;

EID: 0141954927     PISSN: 00989886     EISSN: None     Source Type: Journal    
DOI: 10.1002/cta.244     Document Type: Article
Times cited : (3)

References (14)
  • 5
    • 0026901344 scopus 로고
    • Synthesis techniques for CMOS folded source-coupled logic circuits
    • Maskai S., Kiaei S., Allstot D.J. Synthesis techniques for CMOS folded source-coupled logic circuits. IEEE Journal of Solid-State Circuits 1992; 27(8):1157-1166.
    • (1992) IEEE Journal of Solid-state Circuits , vol.27 , Issue.8 , pp. 1157-1166
    • Maskai, S.1    Kiaei, S.2    Allstot, D.J.3
  • 8
    • 0015025121 scopus 로고
    • MOS models and circuit simulation
    • Meyer J.E. MOS models and circuit simulation. RCA Review 1971; 32:42-63.
    • (1971) RCA Review , vol.32 , pp. 42-63
    • Meyer, J.E.1
  • 11
    • 85039605238 scopus 로고    scopus 로고
    • Wolfram Research Inc., URL http://www.wolfram.com
  • 13
    • 0032073424 scopus 로고    scopus 로고
    • Macromodel construction and verification
    • Kayssi AI. Macromodel construction and verification. IEEE Circuits and Devices 1998; 14(3):34-39.
    • (1998) IEEE Circuits and Devices , vol.14 , Issue.3 , pp. 34-39
    • Kayssi, A.I.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.