Multistage interconnection networks for parallel viterbi decoders

IEEE Transactions on Communications

Volumn 51, Issue 9, 2003, Pages 1536-1545

  Akopian, David ^a   Takala, Jarmo ^b   Saarinen, Jukka ^a,b   Astola, Jaakko ^b  

^a NOKIA RESEARCH CENTER   (United States)

^b TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

Multistage interconnection networks (MINs); Viterbi algorithm (VA) architecture; Viterbi decoding

Indexed keywords

COMPUTATIONAL COMPLEXITY; DECODING; INTERCONNECTION NETWORKS; MATHEMATICAL OPERATORS; PARALLEL ALGORITHMS; SHIFT REGISTERS; SIGNAL ENCODING;

MULTISTAGE INTERCONNECTION NETWORKS; PARALLEL VITERBI DECODERS; VITERBI ALGORITHM; VITERBI DECODING;

TELECOMMUNICATION NETWORKS;

EID: 0141920351     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCOMM.2003.816998     Document Type: Article

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